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    Shared Error Correction Code (ECC) Circuitry
    21.
    发明申请
    Shared Error Correction Code (ECC) Circuitry 有权

    公开(公告)号：US20220066874A1

    公开(公告)日：2022-03-03

    申请号：US17412050

    申请日：2021-08-25

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

    IPC: G06F11/10 ,  G11C11/409

    Abstract: Described apparatuses and methods provide error correction code (ECC) circuitry that is shared between two or more memory banks of a memory, such as a low-power dynamic random-access memory (DRAM). A memory device may include one or more dies, and a die can have multiple memory banks. The ECC circuitry can service at least two memory banks by producing ECC values based on respective data stored in the two memory banks. By sharing the ECC circuitry, instead of including a per-bank ECC engine, a total die area allocated to ECC functionality can be reduced. Thus, the ECC circuitry can be elevated from a one-bit ECC algorithm to a multibit ECC algorithm, which may increase data reliability. In some cases, memory architecture may operate in environments in which a masked-write command or an internal read-modify-write operation is precluded, including with shared ECC circuitry.

    Adaptive Memory Refresh Control
    22.
    发明申请
    Adaptive Memory Refresh Control 有权

    公开(公告)号：US20220066700A1

    公开(公告)日：2022-03-03

    申请号：US17458068

    申请日：2021-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

    IPC: G06F3/06

    Abstract: Systems, apparatuses, and methods related to a memory device and an associated host device are described. The memory device and the host device can include control logic that allow the memory device and host device to share refresh-timing information, which may allow either the memory device or the host, or both, to manage operations during time that is dedicated to, but unused for, refresh or self-refresh operations. Refresh-timing information shared from the host device may indicate elapsed time since the host device issued a refresh command to the memory device and/or how much time remains before the host device is scheduled to issue another refresh command. Refresh-timing information shared from the memory device may indicate elapsed time since the memory device performed a self-refresh operation and/or how much time remains before the memory device is scheduled to initiate or undergo another self-refresh operation.

    Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal
    23.
    发明授权
    Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal 有权

    公开(公告)号：US10825495B2

    公开(公告)日：2020-11-03

    申请号：US16735543

    申请日：2020-01-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

    IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076

    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

    MEMORY DEVICES AND SYSTEMS WITH PARALLEL IMPEDANCE ADJUSTMENT CIRCUITRY AND METHODS FOR OPERATING THE SAME
    24.
    发明申请
    MEMORY DEVICES AND SYSTEMS WITH PARALLEL IMPEDANCE ADJUSTMENT CIRCUITRY AND METHODS FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20200159684A1

    公开(公告)日：2020-05-21

    申请号：US16752551

    申请日：2020-01-24

    Applicant: Micron Technology, Inc.

    Inventor： Hyun Yoo Lee

    IPC: G06F13/40 ,  G11C29/50 ,  G11C29/02 ,  G06F13/00 ,  H04L25/02 ,  H05K1/02

    Abstract: Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

    APPARATUSES AND METHODS FOR PROVIDING ACTIVE AND INACTIVE CLOCK SIGNALS
    27.
    发明申请
    APPARATUSES AND METHODS FOR PROVIDING ACTIVE AND INACTIVE CLOCK SIGNALS 审中-公开

    公开(公告)号：US20190189168A1

    公开(公告)日：2019-06-20

    申请号：US16273562

    申请日：2019-02-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hyun Yoo Lee

    IPC: G11C7/22

    CPC classification number: G11C7/222 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4097

    Abstract: Apparatuses and methods for providing active an inactive clock signals are disclosed. An example apparatus includes an input clock buffer and a clock divider circuit. The input clock buffer includes a receiver circuit configured to receive first and second clock signals or first and second constant voltages. The receiver circuit is further configured to provide first and second output signals based on the complementary clock signals or the first and second constant voltages. The first and second clock signals are complementary and the second constant voltage is less than the first constant voltage. The clock divider circuit is configured to receive the first and second output signals and provide multiphase clock signals based on the first and second output signals from the input clock buffer.

    APPARATUSES AND METHODS FOR DETERMINING A PHASE RELATIONSHIP BETWEEN AN INPUT CLOCK SIGNAL AND A MULTIPHASE CLOCK SIGNAL
    30.
    发明申请
    APPARATUSES AND METHODS FOR DETERMINING A PHASE RELATIONSHIP BETWEEN AN INPUT CLOCK SIGNAL AND A MULTIPHASE CLOCK SIGNAL 审中-公开

    公开(公告)号：US20180247683A1

    公开(公告)日：2018-08-30

    申请号：US15445935

    申请日：2017-02-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

    IPC: G11C7/22 ,  G11C8/10 ,  G11C8/18

    CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C11/4076 ,  G11C2207/2272

    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

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