公开(公告)号：US11262941B2

公开(公告)日：2022-03-01

申请号：US16413475

申请日：2019-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  John D. Porter

IPC: G06F3/06 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4074

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.

公开(公告)号：US11127449B2

公开(公告)日：2021-09-21

申请号：US15962938

申请日：2018-04-25

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri ,  Suryanarayana B. Tatapudi ,  John D. Porter

IPC: G11C11/22

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

公开(公告)号：US10437514B2

公开(公告)日：2019-10-08

申请号：US15722769

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  John D. Porter

IPC: G06F3/06 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4074

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.

公开(公告)号：US20190265913A1

公开(公告)日：2019-08-29

申请号：US16413475

申请日：2019-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  John D. Porter

IPC: G06F3/06

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing, an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.

公开(公告)号：US10229728B2

公开(公告)日：2019-03-12

申请号：US15910867

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  John D. Porter

IPC: G11C11/00 ,  G11C11/406 ,  G11C11/408

Abstract: Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. Additional apparatuses and methods are described.

公开(公告)号：US10153030B2

公开(公告)日：2018-12-11

申请号：US15590972

申请日：2017-05-09

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C7/10

Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

公开(公告)号：US20180330775A1

公开(公告)日：2018-11-15

申请号：US15590972

申请日：2017-05-09

Applicant: Micron Technology, Inc.

Inventor： HYUN YOO LEE ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2207/2272

Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

公开(公告)号：US20250087254A1

公开(公告)日：2025-03-13

申请号：US18958701

申请日：2024-11-25

Applicant: Micron Technology, Inc.

Inventor： Si Hong Kim ,  John D. Porter

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/08

Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense components. Moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. For example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. Such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.

公开(公告)号：US12183420B2

公开(公告)日：2024-12-31

申请号：US17899849

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Si Hong Kim ,  John D. Porter

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/08

Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense components. Moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. For example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. Such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.

公开(公告)号：US20240369632A1

公开(公告)日：2024-11-07

申请号：US18772690

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Kenneth M. Curewitz ,  Jaime Cummins ,  John D. Porter ,  Bryce D. Cook ,  Jeffrey P. Wright

IPC: G01R31/319 ,  G01R31/3185

Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.