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公开(公告)号：US12080330B2
公开(公告)日：2024-09-03
申请号：US17899859
申请日：2022-08-31
Applicant: Micron Technology, Inc.
Inventor： Si Hong Kim , John D. Porter
IPC: G11C11/22
CPC classification number: G11C11/2273 , G11C11/221 , G11C11/2257
Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.
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公开(公告)号：US20240071456A1
公开(公告)日：2024-02-29
申请号：US17899859
申请日：2022-08-31
Applicant: Micron Technology, Inc.
Inventor： Si Hong Kim , John D. Porter
IPC: G11C11/22
CPC classification number: G11C11/2273 , G11C11/221 , G11C11/2257
Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.
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公开(公告)号：US20240395303A1
公开(公告)日：2024-11-28
申请号：US18794453
申请日：2024-08-05
Applicant: Micron Technology, Inc.
Inventor： Si Hong Kim , John D. Porter
IPC: G11C11/22
Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.
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公开(公告)号：US20230146544A1
公开(公告)日：2023-05-11
申请号：US17523312
申请日：2021-11-10
Applicant: Micron Technology, Inc.
Inventor： Mijo Kim , Scott E. Smith , Si Hong Kim
CPC classification number: G11C7/1093 , G11C7/1066 , G11C7/20 , G11C7/106 , G11C7/1087 , G11C8/18
Abstract: Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.
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公开(公告)号：US20250087254A1
公开(公告)日：2025-03-13
申请号：US18958701
申请日：2024-11-25
Applicant: Micron Technology, Inc.
Inventor： Si Hong Kim , John D. Porter
Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense components. Moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. For example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. Such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.
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Patent Agency Ranking
公开(公告)号：US12183420B2
公开(公告)日：2024-12-31
申请号：US17899849
申请日：2022-08-31
Applicant: Micron Technology, Inc.
Inventor： Si Hong Kim , John D. Porter
Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense components. Moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. For example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. Such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.
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公开(公告)号：US20230178139A1
公开(公告)日：2023-06-08
申请号：US17922199
申请日：2020-05-29
Applicant: Micron Technology, Inc.
Inventor： Si Hong Kim , Ki-Jun Nam , Zhi Qi Huang , John David Porter
IPC: G11C11/4076
CPC classification number: G11C11/4076
Abstract: A system (100) for providing a timing signal with tunable temperature dependency in an electronic device may include a timing circuit (102) and an initial setting circuit (104). The timing circuit (102) may include a delay stage (106) and a gate stage (108). The delay stage (106) may be configured to receive an input signal and to produce a delayed signal by introducing a delay to the input signal. The gate stage (108) may be configured to receive the delayed signal and a threshold setting signal, to produce an output signal using the delayed signal and a logic threshold, and to set an initial value of the logic threshold according to the threshold setting signal. The initial setting circuit (104) may be configured to allow the threshold setting signal to be tuned for providing the time delay with a specified temperature dependency.
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公开(公告)号：US11226646B2
公开(公告)日：2022-01-18
申请号：US16891963
申请日：2020-06-03
Applicant: Micron Technology, Inc.
Inventor： Si Hong Kim , Ki-Jun Nam
Abstract: An electronic device may include a main circuit including multiple sub-circuits powered by a direct-current (DC) power supply circuit. The main circuit has a main circuit current demand being a time-varying demand for a DC voltage-regulated supply current being a function of a number of the sub-circuits being active. The DC power supply circuit may include multiple DC voltage regulators to provide the main circuit with the supply current and a command decoding and power management circuit to control enablement of the voltage regulators. The command decoding and power management circuit may be configured to detect an instant value of the main circuit current demand and to selectively enable one or more of the voltage regulators based on the detected instant value.
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公开(公告)号：US20240071431A1
公开(公告)日：2024-02-29
申请号：US17899849
申请日：2022-08-31
Applicant: Micron Technology, Inc.
Inventor： Si Hong Kim , John D. Porter
CPC classification number: G11C7/1039 , G11C7/1012 , G11C7/222 , G11C8/08
Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense components. Moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. For example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. Such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.
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公开(公告)号：US11848070B2
公开(公告)日：2023-12-19
申请号：US17523312
申请日：2021-11-10
Applicant: Micron Technology, Inc.
Inventor： Mijo Kim , Scott E. Smith , Si Hong Kim
CPC classification number: G11C7/1093 , G11C7/106 , G11C7/1066 , G11C7/1087 , G11C7/20 , G11C8/18
Abstract: Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.
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