公开(公告)号：US20200266189A1

公开(公告)日：2020-08-20

申请号：US16866723

申请日：2020-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Smith

IPC: H01L27/02 ,  G11C7/02 ,  G11C16/04 ,  G11C16/22 ,  G11C16/16

Abstract: Apparatus having an array of memory cells might include a first transistor having a control gate, a first source/drain connected to a first contact for connection to peripheral circuitry, and a second source/drain connected to a second contact for connection to a data line selectively connected to a respective set of strings of series-connected memory cells of the array of memory cells; and a second transistor having a control gate, a first source/drain connected to the second contact, and a second source/drain connected to a third contact for connection to a common source selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the data line.

公开(公告)号：US10522547B2

公开(公告)日：2019-12-31

申请号：US15845729

申请日：2017-12-18

Applicant: Micron Technology, Inc.

Inventor： Michael Smith

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L29/36 ,  H01L21/8238 ,  H01L27/108

Abstract: Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.

公开(公告)号：US09847335B2

公开(公告)日：2017-12-19

申请号：US15149774

申请日：2016-05-09

Applicant: Micron Technology, Inc.

Inventor： Michael Smith

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L29/36 ,  H01L21/8238 ,  H01L27/108

CPC classification number: H01L27/0928 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823892 ,  H01L27/10897 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/36

Abstract: Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.

公开(公告)号：US20160254263A1

公开(公告)日：2016-09-01

申请号：US15149774

申请日：2016-05-09

Applicant: Micron Technology, Inc.

Inventor： Michael Smith

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/108

CPC classification number: H01L27/0928 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823892 ,  H01L27/10897 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/36

Abstract: Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.

Abstract translation: 公开了装置和方法。 一种这样的设备包括具有形成在具有第二类导电性的半导体结构内的第一类型的导电体的阱。 井的边界与水龙头的活动区域相交。

公开(公告)号：US09337333B2

公开(公告)日：2016-05-10

申请号：US14448198

申请日：2014-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L27/105

CPC classification number: H01L29/7833 ,  H01L21/266 ,  H01L27/105 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/423 ,  H01L29/6659

Abstract: A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

Abstract translation: 晶体管包括在具有第一导电类型的半导体上的栅极电介质，栅极电介质上的控制栅极，在具有第一导电类型的半导体中具有第二导电类型的源极和漏极区域，以及具有第二导电类型的条带 半导体具有第一导电类型并且插入在控制栅极和源极和漏极区域中的至少一个之间。