公开(公告)号：US11211382B2

公开(公告)日：2021-12-28

申请号：US16895927

申请日：2020-06-08

Applicant: Micron Technology, Inc.

Inventor： Michael Smith

IPC: H01L21/761 ,  H01L21/74 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/266 ,  H01L21/223 ,  H01L21/265 ,  H01L21/762 ,  H01L21/02

Abstract: Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well has an edge that is substantially beneath an edge of an active area of a tap to the well.

公开(公告)号：US10163893B1

公开(公告)日：2018-12-25

申请号：US15687732

申请日：2017-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Smith

IPC: G11C16/04 ,  H01L27/02 ,  G11C16/16 ,  G11C16/08

Abstract: Apparatus including an array of memory cells may include circuit-protection devices that may include first and second circuit-protection units, a first gate having a first source/drain connected to a first node of the first circuit-protection unit, and a second gate having a first source/drain connected to a first node of the second circuit-protection unit, wherein a second source/drain of the first gate is connected to a second source/drain of the second gate.

公开(公告)号：US20150021707A1

公开(公告)日：2015-01-22

申请号：US14507573

申请日：2014-10-06

Applicant: Micron Technology, Inc.

Inventor： Vladimir Mikhalev ,  Michael Smith ,  Henry J. Fulford ,  Puneet Sharma ,  Zia A. Shafi

IPC: H01L23/552 ,  H03K17/16 ,  H01L29/45 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L23/552 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/088 ,  H01L29/402 ,  H01L29/404 ,  H01L29/45 ,  H01L29/7833 ,  H01L2924/0002 ,  H03K17/161 ,  H03K17/162 ,  H01L2924/00

Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.

Abstract translation: 描述半导体器件以及包括它们的方法和系统。 一种这样的器件包括在半导体材料中的扩散区域，耦合到扩散区域的端子和耦合到端子并且从端子在扩散区域上延伸以屏蔽扩散区域的场板。 还描述了另外的实施例。

公开(公告)号：US11335675B2

公开(公告)日：2022-05-17

申请号：US17128752

申请日：2020-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Smith

IPC: H01L27/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/22 ,  G11C7/02 ,  G11C16/08

Abstract: Circuit-protection devices might include first and second circuit-protection units each comprising a first node and a second node, a first field-effect transistor having a first source/drain connected to the first node of the first circuit-protection unit, and a second field-effect transistor having a first source/drain connected to the first node of the second circuit-protection unit, wherein a second source/drain of the first field-effect transistor merges with a second source/drain of the second field-effect transistor.

公开(公告)号：US10892259B2

公开(公告)日：2021-01-12

申请号：US16866723

申请日：2020-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Smith

IPC: H01L27/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/22 ,  G11C7/02 ,  G11C16/08

Abstract: Apparatus having an array of memory cells might include a first transistor having a control gate, a first source/drain connected to a first contact for connection to peripheral circuitry, and a second source/drain connected to a second contact for connection to a data line selectively connected to a respective set of strings of series-connected memory cells of the array of memory cells; and a second transistor having a control gate, a first source/drain connected to the second contact, and a second source/drain connected to a third contact for connection to a common source selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the data line.

公开(公告)号：US20200119139A1

公开(公告)日：2020-04-16

申请号：US16159180

申请日：2018-10-12

Applicant: Micron Technology, Inc.

Inventor： Michael Smith

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/265

Abstract: Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well has an edge that is substantially beneath an edge of an active area of a tap to the well.

公开(公告)号：US09337266B2

公开(公告)日：2016-05-10

申请号：US14502804

申请日：2014-09-30

Applicant: Micron Technology, Inc.

Inventor： Michael Smith

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L29/36

CPC classification number: H01L27/0928 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823892 ,  H01L27/10897 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/36

Abstract: Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.

Abstract translation: 公开了装置和方法。 一种这样的设备包括具有形成在具有第二类导电性的半导体结构内的第一类型的导电体的阱。 井的边界与水龙头的活动区域相交。

公开(公告)号：US20140339648A1

公开(公告)日：2014-11-20

申请号：US14448198

申请日：2014-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/266 ,  H01L27/105 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/423 ,  H01L29/6659

Abstract: A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

Abstract translation: 晶体管包括在具有第一导电类型的半导体上的栅极电介质，栅极电介质上的控制栅极，在具有第一导电类型的半导体中具有第二导电类型的源极和漏极区域，以及具有第二导电类型的条带 半导体具有第一导电类型并且插入在控制栅极和源极和漏极区域中的至少一个之间。

公开(公告)号：US20210028171A1

公开(公告)日：2021-01-28

申请号：US16895927

申请日：2020-06-08

Applicant: Micron Technology, Inc.

Inventor： Michael Smith

IPC: H01L27/092 ,  H01L21/761 ,  H01L21/74

Abstract: Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well has an edge that is substantially beneath an edge of an active area of a tap to the well.

公开(公告)号：US20200212040A1

公开(公告)日：2020-07-02

申请号：US16730169

申请日：2019-12-30

Applicant: Micron Technology, Inc.

Inventor： Michael Smith

IPC: H01L27/092 ,  H01L27/108 ,  H01L21/8238 ,  H01L29/36 ,  H01L29/10 ,  H01L21/762 ,  H01L21/265 ,  H01L29/06

Abstract: Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.