公开(公告)号：US07154300B2

公开(公告)日：2006-12-26

申请号：US10744084

申请日：2003-12-24

申请人： Mark A. Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

发明人： Mark A. Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

IPC分类号： H03K19/0175 ,  G06F13/00 ,  G11C7/00

CPC分类号： H04L25/0278 ,  H04L25/028

摘要： A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

摘要翻译： 提供动态总线架构。 这可以包括耦合到总线线路的编码电路和耦合到总线线路的解码器电路。 编码器电路可以接收输入信号并在总线上生成编码信号。 解码器电路可以从总线接收编码信号并产生原始未编码信号。 编码器电路可以包括第一触发器电路，其基于来自总线的时钟信号来存储来自总线的先前输入信号。 此外，解码器电路可以包括具有时钟输入的第二触发器电路，以从总线接收编码信号作为时钟输入。

公开(公告)号：US07603398B2

公开(公告)日：2009-10-13

申请号：US11094811

申请日：2005-03-31

申请人： Atul Maheshwari ,  Sanu K. Matthew ,  Mark A. Anders ,  Ram Krishnamurthy

发明人： Atul Maheshwari ,  Sanu K. Matthew ,  Mark A. Anders ,  Ram Krishnamurthy

IPC分类号： G06F7/00 ,  G06F15/00

CPC分类号： G06F9/3869 ,  G06F7/74

摘要： For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.

摘要翻译： 对于一个公开的实施例，转换器将2N位数据转换成指示具有预定逻辑值的数据中的位数的N位值。 转换器包括N个比较器，每个比较器确定具有预定逻辑值的数据中的位数是否超过多个参考值中的相应一个。 基于比较器的输出产生N位值。 对于另一个公开的实施例，第一延迟元件基于具有预定逻辑值的数据值中的位数来延迟信号，并且第二延迟元件基于具有预定逻辑的参考值中的位数来延迟该信号 值。 比较器然后基于延迟信号产生位值。

公开(公告)号：US20080104164A1

公开(公告)日：2008-05-01

申请号：US11586810

申请日：2006-10-26

申请人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

IPC分类号： G06F7/52

CPC分类号： G06F7/5324 ,  G06F2207/3828

摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

公开(公告)号：US07196548B2

公开(公告)日：2007-03-27

申请号：US10927574

申请日：2004-08-25

申请人： Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

发明人： Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC分类号： H03K19/094 ,  H03K17/16

CPC分类号： H03K3/356156 ,  H03K3/356191

摘要： A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

摘要翻译： 本文描述了具有新颖的静态无功接收器电路的单端电流感测总线。 在一个实施例中，接收器电路示例包括锁存电路，以在响应于输入的评估阶段期间锁存第一输出和第二输出的值;耦合到锁存电路的预充电电路以预充电锁存电路 以及耦合到预充电电路和锁存电路的静态功耗阻塞（SPDB）电路，以在预充电阶段期间基本上阻止静态功率消散。 还描述了其它方法和装置。

公开(公告)号：US06522186B2

公开(公告)日：2003-02-18

申请号：US09893067

申请日：2001-06-27

申请人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

发明人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.

摘要翻译： 分层时钟分配系统包括将时钟信号分配到多个区域时钟网格的全局时钟网格。 然后，每个区域时钟网格将信号分配给多个对应的负载。 区域时钟网格利用相关的时钟技术将时钟信号分配给相应的负载。 基于时钟信号的周期性，全球电网实现了低偏移，而不是驻波的优势。 区域时钟网格内的终端电气距离优选保持较低，以避免在区域网格上发生相变区域。 在一种方法中，区域网格以对称方式被驱动在多个点，以减少到终止的电距离。

公开(公告)号：US06909127B2

公开(公告)日：2005-06-21

申请号：US09893023

申请日：2001-06-27

申请人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

发明人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

IPC分类号： H01L23/522 ,  H01L27/10

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.