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105 条记录 (耗时 0.023 秒)

    Reconfigurable SIMD vector processing system
    1.
    发明申请
    Reconfigurable SIMD vector processing system 有权
    可重构SIMD矢量处理系统

    公开(公告)号：US20080104164A1

    公开(公告)日：2008-05-01

    申请号：US11586810

    申请日：2006-10-26

    申请人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F2207/3828

    摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

    摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

    Encoder and decoder circuits for dynamic bus
    2.
    发明授权
    Encoder and decoder circuits for dynamic bus 有权
    用于动态总线的编码器和解码器电路

    公开(公告)号：US07154300B2

    公开(公告)日：2006-12-26

    申请号：US10744084

    申请日：2003-12-24

    申请人： Mark A. Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    发明人： Mark A. Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC分类号： H03K19/0175 ,  G06F13/00 ,  G11C7/00

    CPC分类号： H04L25/0278 ,  H04L25/028

    摘要： A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

    摘要翻译： 提供动态总线架构。 这可以包括耦合到总线线路的编码电路和耦合到总线线路的解码器电路。 编码器电路可以接收输入信号并在总线上生成编码信号。 解码器电路可以从总线接收编码信号并产生原始未编码信号。 编码器电路可以包括第一触发器电路，其基于来自总线的时钟信号来存储来自总线的先前输入信号。 此外，解码器电路可以包括具有时钟输入的第二触发器电路，以从总线接收编码信号作为时钟输入。

    Reconfigurable SIMD vector processing system
    3.
    发明授权
    Reconfigurable SIMD vector processing system 有权
    可重构SIMD矢量处理系统

    公开(公告)号：US07519646B2

    公开(公告)日：2009-04-14

    申请号：US11586810

    申请日：2006-10-26

    申请人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F2207/3828

    摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

    摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT
    4.
    发明申请
    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT 有权
    紧凑型低功耗高级加密标准电路

    公开(公告)号：US20150086007A1

    公开(公告)日：2015-03-26

    申请号：US14035508

    申请日：2013-09-24

    申请人： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    发明人： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC分类号： H04L9/30

    CPC分类号： H04L9/0631 ,  H04L2209/24

    摘要： Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.

    摘要翻译： 公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。 在一个实施例中，装置包括具有替换盒和累加器的加密单元。 替代方案是对每个时钟周期的一个字节执行替换操作。 累加器将累积四个字节，并在四个时钟周期内执行混合列操作。 加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。

    Encoder and decoder circuits for dynamic bus
    7.
    发明申请
    Encoder and decoder circuits for dynamic bus 有权
    用于动态总线的编码器和解码器电路

    公开(公告)号：US20050146357A1

    公开(公告)日：2005-07-07

    申请号：US10744084

    申请日：2003-12-24

    申请人： Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC分类号： H03K19/0175 ,  H04L25/02

    CPC分类号： H04L25/0278 ,  H04L25/028

    摘要： A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

    摘要翻译： 提供动态总线架构。 这可以包括耦合到总线线路的编码电路和耦合到总线线路的解码器电路。 编码器电路可以接收输入信号并在总线上生成编码信号。 解码器电路可以从总线接收编码信号并产生原始未编码信号。 编码器电路可以包括第一触发器电路，其基于来自总线的时钟信号来存储来自总线的先前输入信号。 此外，解码器电路可以包括具有时钟输入的第二触发器电路，以从总线接收编码信号作为时钟输入。

    PRIORITY-BASED ROUTING
    9.
    发明申请
    PRIORITY-BASED ROUTING 有权
    优先级路由

    公开(公告)号：US20150188829A1

    公开(公告)日：2015-07-02

    申请号：US14141356

    申请日：2013-12-26

    申请人： Sudhir Satpathy ,  Himanshu Kaul ,  Mark Anders ,  Sanu Mathew ,  Gregory Chen ,  Ram Krishnamurthy

    发明人： Sudhir Satpathy ,  Himanshu Kaul ,  Mark Anders ,  Sanu Mathew ,  Gregory Chen ,  Ram Krishnamurthy

    IPC分类号： H04L12/833 ,  H04L12/933 ,  H04L12/725

    CPC分类号： H04L47/2458 ,  H04L45/30 ,  H04L47/56 ,  H04L47/6275 ,  H04L49/109

    摘要： Disclosed herein is a router configured for priority-based routing. The router is configured to receive a plurality of packets, wherein each packet is assigned a priority value. The router includes an output circuit configured to select the packet with the highest priority value. The output circuit is configured to forward the priority value of the selected packet to a second router. The output circuit is configured to transfer the selected packet to the second router when the link between the first router and the second router is available.

    摘要翻译： 这里公开了配置用于基于优先级路由的路由器。 路由器被配置为接收多个分组，其中每个分组被分配优先级值。 路由器包括配置为选择具有最高优先级值的分组的输出电路。 输出电路被配置为将所选择的分组的优先级值转发给第二路由器。 输出电路被配置为当第一路由器和第二路由器之间的链路可用时将所选择的分组传送到第二路由器。