公开(公告)号：US08564364B2

公开(公告)日：2013-10-22

申请号：US13071325

申请日：2011-03-24

Applicant: Fabrice Marinet ,  Mathieu Lisart

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: H01L27/00 ,  G05F3/08

CPC classification number: G06F1/26 ,  G06F21/72 ,  G06K19/07309 ,  H01L21/76224 ,  H01L23/576 ,  H01L2924/0002 ,  H03K3/84 ,  H03K19/003 ,  H04L9/004 ,  H04L2209/12 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method for detecting an attack in an electronic microcircuit comprises: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage.

Abstract translation: 一种用于检测电子微电路中的攻击的方法，包括：在衬底中形成微电路，在衬底中形成与衬底电隔离的第一阱，由第二阱和嵌入阱形成第一阱和第二阱中的数据 处理电路，包括形成在第一阱中的接地端子和形成在第二阱中的电源端子，并且当数据处理电路的接地或电源端子处的电压超过阈值电压时激活检测信号。

公开(公告)号：US20110234307A1

公开(公告)日：2011-09-29

申请号：US13071325

申请日：2011-03-24

Applicant: Fabrice Marinet ,  Mathieu Lisart

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: G05F3/02 ,  G01R19/00

CPC classification number: G06F1/26 ,  G06F21/72 ,  G06K19/07309 ,  H01L21/76224 ,  H01L23/576 ,  H01L2924/0002 ,  H03K3/84 ,  H03K19/003 ,  H04L9/004 ,  H04L2209/12 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The disclosure relates to a method for detecting an attack in an electronic microcircuit, comprising: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage.

Abstract translation: 本发明涉及一种用于检测电子微电路中的攻击的方法，包括：在衬底中形成所述微电路，在所述衬底中形成第一阱，所述第一阱与所述衬底电隔离，由第二阱和嵌入阱形成， 和第二阱，数据处理电路包括形成在第一阱中的接地端子和形成在第二阱中的电源端子，并且当数据处理电路的接地或电源端子处的电压超过阈值时启动检测信号 电压。

公开(公告)号：US20110153245A1

公开(公告)日：2011-06-23

申请号：US12969266

申请日：2010-12-15

Applicant: Pascal FORNARA ,  Mathieu Lisart

Inventor： Pascal FORNARA ,  Mathieu Lisart

IPC: G06F19/00

CPC classification number: G06K19/067 ,  H01L23/48 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2223/54446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes non-volatile storage configured to secretly store a digital word, the value of which forms an identification code. The integrated circuit also includes control circuitry configured to receive the digital word and to generate transient electrical currents or transient voltages, the characteristics of which depend on the value of the digital word. There is an electrically conductive network configured to be passed through by the electrical currents or receive the transient voltages so as to generate an electromagnetic field that identifies the integrated circuit.

Abstract translation: 集成电路包括被配置为秘密地存储数字字的非易失性存储器，其数值字形成识别码。 集成电路还包括配置成接收数字字并产生瞬态电流或瞬态电压的控制电路，其特性取决于数字字的值。 存在导电网络，其配置为通过电流通过或接收瞬态电压，以便产生识别集成电路的电磁场。

公开(公告)号：US20110113256A1

公开(公告)日：2011-05-12

申请号：US12942557

申请日：2010-11-09

Applicant: Fabrice Marinet ,  Mathieu Lisart

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: G06F12/14 ,  G06F12/00

CPC classification number: H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

Abstract: The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.

Abstract translation: 该组件包括第一存储器（MM），其包括具有由第一修改实体（K1）修改的内容的第一部分（P1）和具有用第二实体（K2）修改的内容的第二部分（P2），存储装置 （MS）被配置为秘密地存储第一实体（K1），非易失性存储器（NVM）将代表第二实体（K2）的实体信息项存储在由第一指示（INDK2）指定的位置（END）中， 包含在第一存储器的所述第一部分中。

公开(公告)号：US07847581B2

公开(公告)日：2010-12-07

申请号：US12416663

申请日：2009-04-01

Applicant: Mathieu Lisart ,  Vincent Pouget

Inventor： Mathieu Lisart ,  Vincent Pouget

IPC: H03K19/00

CPC classification number: H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part of the active areas and the second surface, a device for biasing the first region, and a device for detecting an increase in the current provided by the biasing device.

Abstract translation: 一种集成电路，包括具有第一和第二相对表面的半导体材料的衬底，并且包括使第一表面平整的有效区域。 集成电路包括防止激光攻击的装置，该保护装置包括至少一个在有效区域和第二表面的至少一部分之间延伸的第一掺杂区域，用于偏置第一区域的装置，以及用于检测 由偏置装置提供的电流增加。

公开(公告)号：US07609568B2

公开(公告)日：2009-10-27

申请号：US11493865

申请日：2006-07-25

Applicant: Mathieu Lisart ,  Nicolas Demange

Inventor： Mathieu Lisart ,  Nicolas Demange

IPC: G11C7/18

CPC classification number: G06F21/556 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/24

Abstract: A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits, so that a processing circuit processes electrical signals of different ranks during different processing cycles. The method can be applied particularly to secure a memory during read phases of the memory and of an integrated circuit with a microprocessor using such a memory.

Abstract translation: 一种方法使用根据用于将电信号分配给处理电路的规则处理电信号的连续循环的并行处理电路来处理并行电信号。 该方法包括在处理周期之间，修改用于将电信号分配给处理电路的规则的步骤，使得处理电路在不同处理周期期间处理不同等级的电信号。 该方法可以特别用于在存储器的读取阶段和使用这种存储器的微处理器的集成电路中保护存储器。

公开(公告)号：US20090251168A1

公开(公告)日：2009-10-08

申请号：US12416663

申请日：2009-04-01

Applicant: Mathieu Lisart ,  Vincent Pouget

Inventor： Mathieu Lisart ,  Vincent Pouget

IPC: H03K19/00 ,  H01L21/265 ,  H01L31/00

CPC classification number: H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part of the active areas and the second surface, a device for biasing the first region, and a device for detecting an increase in the current provided by the biasing device.

Abstract translation: 一种集成电路，包括具有第一和第二相对表面的半导体材料的衬底，并且包括使第一表面平整的有效区域。 集成电路包括防止激光攻击的装置，该保护装置包括至少一个在有效区域和第二表面的至少一部分之间延伸的第一掺杂区域，用于偏置第一区域的装置，以及用于检测 由偏置装置提供的电流增加。

公开(公告)号：US20070002616A1

公开(公告)日：2007-01-04

申请号：US11423852

申请日：2006-06-13

Applicant: Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

Inventor： Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

IPC: G11C11/34

CPC classification number: G11C8/20 ,  G11C7/24 ,  G11C16/22

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract translation: 存储器包括布置在存储器阵列中的存储单元，以及地址解码器，用于根据应用于存储器的读取地址将存储单元选择信号应用于存储器阵列。 存储器包括地址重构电路，其从存储器单元选择信号重建读取地址的至少一部分，并且提供能够检测影响选择信号的错误注入的第一重建地址。 特别但不排他地适用于芯片卡的集成电路。

公开(公告)号：US5978915A

公开(公告)日：1999-11-02

申请号：US573942

申请日：1995-12-18

Applicant: Mathieu Lisart ,  Laurent Sourgen

Inventor： Mathieu Lisart ,  Laurent Sourgen

IPC: G06F12/14 ,  G06F21/02 ,  G06K17/00 ,  G06F11/00 ,  G11C17/00

CPC classification number: G06F12/1425

Abstract: The access to memory words of an integrated circuit is protected by the creation of a decision table that receives addresses of instruction words and/or data words to be protected and that receives also addresses of the control bits of a control word assigned to a word to be protected. It can be shown that this mode of action provides greater security through the use of a decision table made in wired circuit form as well as greater flexibility through the programmable quality of the control words assigned to each memory word to be controlled.

Abstract translation: 通过创建接收要保护的指令字和/或数据字的地址的决定表来保护对集成电路的存储字的访问，并且还接收分配给一个字的控制字的控制位的地址 被保护。 可以看出，这种操作模式通过使用以有线电路形式制定的决策表以及通过分配给要控制的每个存储器字的控制字的可编程质量而具有更大的灵活性来提供更大的安全性。

公开(公告)号：US5666077A

公开(公告)日：1997-09-09

申请号：US257086

申请日：1994-06-09

Applicant: Richard Fournel ,  Mathieu Lisart

Inventor： Richard Fournel ,  Mathieu Lisart

IPC: G01R31/28 ,  G01R19/165 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H01L29/739 ,  H03K5/22

CPC classification number: G01R19/16552 ,  H01L29/7391

Abstract: A Zener diode is used to simplify a circuit for detecting the level of an operating voltage with respect to a specified range of use. The semiconductor junction of this Zener diode is biased alternately by one voltage or another. Under these conditions, the avalanche voltage of this Zener diode changes. The operating voltage to be monitored is connected to the cathode of this Zener diode. If the monitored operating voltage is higher than the avalanche voltage of this Zener diode, the diode alternately conducts. If the operating voltage is outside this range, this diode is either permanently on or permanently off. The variations that result therefrom are detected to report whether the operating voltage is correct.

Abstract translation: 齐纳二极管用于简化用于检测相对于指定使用范围的工作电压电平的电路。 该齐纳二极管的半导体结交替地被一个或多个电压偏置。 在这些条件下，该齐纳二极管的雪崩电压发生变化。 要监控的工作电压连接到该齐纳二极管的阴极。 如果监控的工作电压高于该齐纳二极管的雪崩电压，则二极管交替导通。 如果工作电压在该范围之外，则该二极管永久地处于或永久关闭。 检测由此产生的变化，以报告工作电压是否正确。