公开(公告)号：US20080079712A1

公开(公告)日：2008-04-03

申请号：US11536146

申请日：2006-09-28

Applicant: Eric Oliver Mejdrich ,  Adam James Muff ,  Matthew Ray Tubbs

Inventor： Eric Oliver Mejdrich ,  Adam James Muff ,  Matthew Ray Tubbs

IPC: G06T1/00

CPC classification number: G06T1/20 ,  G06F15/8092 ,  G06T15/005

Abstract: The present invention is generally related to the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.

Abstract translation: 本发明通常涉及图像处理领域，更具体地涉及用于支持图像处理的矢量单元。 描述了双向量单元实现，其中配置了两个向量单元从公共寄存器文件接收数据。 向量单元可以独立地并且同时处理指令。 此外，矢量单元可以适于执行标量运算，从而整合向量和标量处理。 矢量单元还可以被配置为共享资源以执行操作，例如交叉产品操作。

公开(公告)号：US07143126B2

公开(公告)日：2006-11-28

申请号：US10607359

申请日：2003-06-26

Applicant: Gordon Clyde Fossum ,  Stephen Joseph Schwinn ,  Matthew Ray Tubbs

Inventor： Gordon Clyde Fossum ,  Stephen Joseph Schwinn ,  Matthew Ray Tubbs

IPC: G06F1/02

CPC classification number: G06F7/556 ,  G06F7/483

Abstract: A method and apparatus are provided for implementing a power of two estimation function in a general purpose floating-point processor. A floating point number is stored within a memory. The floating point number includes a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits. In response to a floating-point instruction, the mantissa is partitioned into an integer part and a fraction part, based on the exponent bits. A floating-point result is provided by assigning the integer part of the floating point number as an unbiased exponent of the floating-point result, and by utilizing combinational logic hardware for converting the fraction part of the floating point number to a fraction part of the floating point result.

Abstract translation: 提供了一种用于在通用浮点处理器中实现两种估计功能的功率的方法和装置。 浮点数存储在内存中。 浮点数包括符号位，多个指数位和具有隐含位和多个分数位的尾数。 响应于浮点指令，基于指数位将尾数划分为整数部分和分数部分。 通过将浮点数的整数部分分配为浮点结果的无偏指数，并且通过使用组合逻辑硬件将浮点数的分数部分转换为浮点数的分数部分来提供浮点结果 浮点结果。

公开(公告)号：US20160180493A1

公开(公告)日：2016-06-23

申请号：US14574093

申请日：2014-12-17

Applicant: Ryan Scott Haraden ,  Matthew Ray Tubbs ,  Adam James Muff ,  Robert Allen Shearer

Inventor： Ryan Scott Haraden ,  Matthew Ray Tubbs ,  Adam James Muff ,  Robert Allen Shearer

IPC: G06T1/60 ,  H04N13/00

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T2200/28 ,  H04N13/139

Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., a local cache) are described. The pixel data may derive from an image capturing device (e.g., a color camera or a depth camera) in which individual pixel values are not a multiple of eight bits. In some embodiments, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one example, the DMA engine may be configured to identify and label one or more pixels as being within a particular range of pixel values and/or the DMA engine may be configured to label pixels as belonging to one or more pixel groups based on their pixel values.

Abstract translation: 描述了在将像素数据从第一存储器（例如，DRAM）到第二存储器（例如，本地高速缓存）的数据传输期间使用直接存储器访问（DMA）引擎预处理像素数据的方法。 像素数据可以从其中各个像素值不是8位的倍数的图像捕获设备（例如，彩色照相机或深度相机）导出。 在一些实施例中，DMA引擎可以在将像素数据写入第二存储器之前对像素数据执行各种图像处理操作。 在一个示例中，DMA引擎可以被配置为将一个或多个像素识别并标记为在像素值的特定范围内，和/或DMA引擎可以被配置为基于它们的像素组将像素标记为属于一个或多个像素组 像素值。

公开(公告)号：US09021004B2

公开(公告)日：2015-04-28

申请号：US13556464

申请日：2012-07-24

Applicant: Adam James Muff ,  Matthew Ray Tubbs

Inventor： Adam James Muff ,  Matthew Ray Tubbs

IPC: G06F7/48 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30014 ,  G06F9/30181

Abstract: A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG.

Abstract translation: 电路布置和方法将基于硬件的伪随机数生成器（PRNG）耦合到执行单元，使得由PRNG生成的伪随机数可以被选择性地输出到执行单元，以在执行指令期间用作操作数， 执行单元。 PRNG可以耦合到操作数多路复用器的输入，该输入输出到执行单元的操作数输入，使得由提供给执行单元的指令提供的操作数被PRNG生成的伪随机数选择性地覆盖。 此外，提供给执行单元的指令提供的覆盖操作数可以用作PRNG的种子值。

公开(公告)号：US08443027B2

公开(公告)日：2013-05-14

申请号：US11861518

申请日：2007-09-26

Applicant: Adam James Muff ,  Matthew Ray Tubbs

Inventor： Adam James Muff ,  Matthew Ray Tubbs

IPC: G06F7/38

CPC classification number: G06F7/483

Abstract: A method, computer-readable medium, and an apparatus for implementing a floating point weighted average function. The method includes receiving an input containing 2N input values, 2N weights, and an opcode, where N is a positive integer number and each of the input values corresponds to one of the weights. Furthermore, the method also includes using existing dot product circuit function to generate 2N addends by multiplying each of the input values with the corresponding weight. In addition, the method includes generating a sum value by adding the 2N addends, where the sum value includes an exponent value, and generating the weighted average value based on the sum value by decreasing the exponent value by N. In this fashion, the same circuit area may be used to carry out both dot product and weighted average calculations, leading to greater circuit area savings and performance advantages.

Abstract translation: 一种用于实现浮点加权平均函数的方法，计算机可读介质和装置。 该方法包括接收包含2N个输入值，2N个权重和操作码的输入，其中N是正整数，并且每个输入值对应于其中一个权重。 此外，该方法还包括使用现有的点积电路函数，通过将每个输入值与相应的权重相乘来产生2N个加数。 此外，该方法包括通过加上2N加数来产生和值，其中和值包括指数值，并且通过将指数值减小N来基于和值生成加权平均值。以这种方式，相同 电路面积可用于进行点积和加权平均计算，从而实现更大的电路面积节省和性能优势。

公开(公告)号：US08356162B2

公开(公告)日：2013-01-15

申请号：US12050721

申请日：2008-03-18

Applicant: Adam James Muff ,  Matthew Ray Tubbs

Inventor： Adam James Muff ,  Matthew Ray Tubbs

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/30072 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3885

Abstract: An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional write instruction identifies a condition as well as data to be tested against that condition. The data is tested against that condition, and the result of the test is used to selectively enable or disable a write to a target associated with the data dependent conditional write instruction. Then, a write is attempted while the write to the target is enabled or disabled such that the write will update the contents of the target only when the write is selectively enabled as a result of the test. By doing so, dependencies are typically avoided, as is use of an architected condition register that might otherwise introduce branch prediction mispredict penalties, enabling improved performance with z-buffer test and similar types of algorithms.

Abstract translation: 执行单元支持仅当满足特定条件时将数据写入目标的数据相关条件写指令。 在一个实现中，依赖于数据的条件写入指令识别条件以及针对该条件进行测试的数据。 根据该条件测试数据，并且测试结果用于选择性地启用或禁用对与数据相关条件写指令相关联的目标的写入。 然后，当对目标的写入被启用或禁用时，尝试写入，以便只有当作为测试的结果有选择地启用写入时，写入才会更新目标的内容。 通过这样做，通常可以避免依赖关系，因为使用可能会导致分支预测错误处理的架构条件寄存器，可以通过z缓冲区测试和类似类型的算法实现改进的性能。

公开(公告)号：US08350846B2

公开(公告)日：2013-01-08

申请号：US12361019

申请日：2009-01-28

Applicant: Eric Oliver Mejdrich ,  Paul Emery Schardt ,  Robert Allen Shearer ,  Matthew Ray Tubbs

Inventor： Eric Oliver Mejdrich ,  Paul Emery Schardt ,  Robert Allen Shearer ,  Matthew Ray Tubbs

IPC: G06T15/00 ,  G06T15/50 ,  G06T15/60 ,  G06T1/00 ,  G06F17/00

CPC classification number: G06T15/06 ,  G06T17/005

Abstract: A method, program product and system for conducting a ray tracing operation where the rendering compute requirement is reduced or otherwise adjusted in response to a changing vantage point. Aspects may update or reuse an acceleration data structure between frames in response to the changing vantage point. Tree and image construction quality may be adjusted in response to rapid changes in the camera perspective. Alternatively or additionally, tree building cycles may be skipped. All or some of the tree structure may be built in intervals, e.g., after a preset number of frames. More geometric image data may be added per leaf node in the tree in response to an increase in the rate of change. The quality of the rendering algorithm may additionally be reduced. A ray tracing algorithm may decrease the depth of recursion, and generate fewer cast and secondary rays. The ray tracer may further reduce the quality of soft shadows, resolution and global illumination samples, among other quality parameters. Alternatively, tree rebuilding may be skipped entirely in response to a high camera rate of change. Associated processes may create blur between frames to simulate motion blur.

Abstract translation: 一种用于执行光线跟踪操作的方法，程序产品和系统，其中响应于不断变化的有利位置来减少或以其他方式调整渲染计算要求。 响应于不断变化的有利位置，方面可以更新或重新使用帧之间的加速度数据结构。 可以根据相机视角的快速变化来调整树木和图像施工质量。 或者或另外，可以跳过建树循环。 树结构的全部或一些可以以间隔内置，例如在预设数量的帧之后。 响应于变化率的增加，可以在树中的每个叶节点添加更多的几何图像数据。 还可以减少渲染算法的质量。 光线跟踪算法可以减少递归深度，并产生更少的投射和二次光线。 光线跟踪器可以进一步降低软阴影，分辨率和全局照明样本的质量以及其他质量参数。 或者，可以根据高摄像机的变化率来完全地跳过树重建。 相关过程可能会在帧之间产生模糊以模拟运动模糊。

公开(公告)号：US08255443B2

公开(公告)日：2012-08-28

申请号：US12132115

申请日：2008-06-03

Applicant: Adam James Muff ,  Matthew Ray Tubbs

Inventor： Adam James Muff ,  Matthew Ray Tubbs

IPC: G06F7/58

CPC classification number: G06F9/3851 ,  G06F9/30014 ,  G06F9/30181

Abstract: A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG. In many instances, an instruction executed by an execution unit may be able to perform an arithmetic operation using both an operand specified by the instruction and a pseudorandom number generated by the PRNG during the execution of the instruction, so that the generation of the pseudorandom number and the performance of the arithmetic operation occur during a single pass of an execution unit.

Abstract translation: 电路布置和方法将基于硬件的伪随机数生成器（PRNG）耦合到执行单元，使得由PRNG生成的伪随机数可以被选择性地输出到执行单元，以在执行指令期间用作操作数， 执行单元。 PRNG可以耦合到操作数多路复用器的输入，该输入输出到执行单元的操作数输入，使得由提供给执行单元的指令提供的操作数被PRNG生成的伪随机数选择性地覆盖。 此外，提供给执行单元的指令提供的覆盖操作数可以用作PRNG的种子值。 在许多情况下，执行单元执行的指令可以在执行指令期间使用由指令指定的操作数和由PRNG生成的伪随机数来执行算术运算，从而生成伪随机数 并且算术运算的执行在执行单元的单次通过期间发生。

公开(公告)号：US08243073B2

公开(公告)日：2012-08-14

申请号：US12361006

申请日：2009-01-28

Applicant: Eric Oliver Mejdrich ,  Paul Emery Schardt ,  Robert Allen Shearer ,  Matthew Ray Tubbs

Inventor： Eric Oliver Mejdrich ,  Paul Emery Schardt ,  Robert Allen Shearer ,  Matthew Ray Tubbs

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/40 ,  G06T15/10 ,  G06T15/20 ,  G06T15/06

CPC classification number: G06T15/06 ,  G06T17/005

Abstract: A method, program product and system for conducting a ray tracing operation where the rendering compute requirement is reduced by varying the size of bounding volumes into which image data is divided and/or by varying a number of primitives included within nodes of an acceleration data structure that correspond to the bounding volumes.

Abstract translation: 一种用于进行光线跟踪操作的方法，程序产品和系统，其中通过改变分割图像数据的边界体积的大小和/或通过改变包括在加速度数据结构的节点内的原始数量来减少渲染计算要求 对应于边界体积。

公开(公告)号：US07814299B2

公开(公告)日：2010-10-12

申请号：US12274560

申请日：2008-11-20

Applicant: Mark Joseph Hickey ,  Adam James Muff ,  Matthew Ray Tubbs ,  Charles David Wait

Inventor： Mark Joseph Hickey ,  Adam James Muff ,  Matthew Ray Tubbs ,  Charles David Wait

IPC: G06F9/30

CPC classification number: G06F9/30098 ,  G06F9/3016 ,  G06F9/3832

Abstract: A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.

Abstract translation: 一种电路布置和方法支持指令目标历史的寄存器地址索引，由此由指令使用的寄存器地址使用先前目标寄存器地址的目标历史表和由目标历史表中的索引值提供的索引进行解码 指示。 指令可以包括标识先前使用的寄存器地址的至少一个索引值。 在执行指令期间，从指令中检索索引，然后使用索引从目标历史表中检索一个寄存器地址。