公开(公告)号：US11641788B2

公开(公告)日：2023-05-02

申请号：US17116559

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  Dale W. Collins ,  Fabio Pellizzer

IPC: H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for a resistive interface material are described. A memory device may be fabricated using a sequence of steps that include forming a stack of materials by depositing a first metal layer, depositing a first electrode layer on the metal layer, depositing a memory material on the first electrode layer to form one or more memory cells, depositing a second electrode layer on the memory material, and depositing a second metal layer on the second electrode layer. A lamina (or multiple) having a relatively high resistivity may be included in the stack of materials to reduce or eliminate a current spike that may otherwise occur across the memory cells during an access operation.

公开(公告)号：US20230113573A1

公开(公告)日：2023-04-13

申请号：US18048633

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

公开(公告)号：US20220181549A1

公开(公告)日：2022-06-09

申请号：US17116559

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  Dale W. Collins ,  Fabio Pellizzer

IPC: H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for a resistive interface material are described. A memory device may be fabricated using a sequence of steps that include forming a stack of materials by depositing a first metal layer, depositing a first electrode layer on the metal layer, depositing a memory material on the first electrode layer to form one or more memory cells, depositing a second electrode layer on the memory material, and depositing a second metal layer on the second electrode layer. A lamina (or multiple) having a relatively high resistivity may be included in the stack of materials to reduce or eliminate a current spike that may otherwise occur across the memory cells during an access operation.

公开(公告)号：US10256406B2

公开(公告)日：2019-04-09

申请号：US15155618

申请日：2016-05-16

Applicant: Micron Technology, Inc.

Inventor： Dale W. Collins ,  Andrea Gotti ,  F. Daniel Gealy ,  Tuman E. Allen ,  Swapnil Lengade

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

公开(公告)号：US10090462B2

公开(公告)日：2018-10-02

申请号：US14960953

申请日：2015-12-07

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy ,  Lei Bi ,  Beth R. Cook ,  Dale W. Collins

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/02 ,  G11C13/00

Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US09431606B1

公开(公告)日：2016-08-30

申请号：US14825087

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy ,  Dale W. Collins ,  Christopher W. Petz ,  Beth R. Cook

IPC: H01L45/00

CPC classification number: H01L45/1266 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/14

Abstract: Some embodiments include a memory cell having a pair of electrodes, and a plurality of switching levels between the electrodes. Each switching level has an ion buffer region and a dielectric region. At least one switching level differs from another switching level in one or both of thickness and composition of the ion buffer region and/or the dielectric region.

Abstract translation: 一些实施例包括具有一对电极的存储单元和电极之间的多个开关电平。 每个开关电平具有离子缓冲区和电介质区。 至少一个开关电平与离子缓冲区域和/或电介质区域的厚度和组成中的一个或两个中的另一个开关电平不同。

公开(公告)号：US11990370B2

公开(公告)日：2024-05-21

申请号：US18048633

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76883 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

公开(公告)号：US20230270025A1

公开(公告)日：2023-08-24

申请号：US17676708

申请日：2022-02-21

Applicant: Micron Technology, Inc.

Inventor： Dale W. Collins ,  Paolo Fantini ,  Lorenzo Fratin ,  Enrico Varesi

IPC: G11C16/10 ,  G11C16/04 ,  C01B19/04 ,  C01B17/02

CPC classification number: G11C16/102 ,  G11C16/045 ,  C01B19/04 ,  C01B17/0243 ,  G11C16/0466 ,  G11C2216/02

Abstract: Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).

公开(公告)号：US20180374745A1

公开(公告)日：2018-12-27

申请号：US16103012

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Dale W. Collins ,  Joe Lindgren

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material. Some embodiments include semiconductor constructions having a metal nitride liner along sidewall peripheries of an opening, and having copper-containing material within the opening and directly against the metal nitride liner.

公开(公告)号：US10121697B2

公开(公告)日：2018-11-06

申请号：US14930524

申请日：2015-11-02

Applicant: Micron Technology, Inc.

Inventor： Dale W. Collins ,  Joe Lindgren

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material. Some embodiments include semiconductor constructions having a metal nitride liner along sidewall peripheries of an opening, and having copper-containing material within the opening and directly against the metal nitride liner.