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    REPAIR OPERATION TECHNIQUES
    22.
    发明申请
    REPAIR OPERATION TECHNIQUES 有权

    公开(公告)号：US20230125544A1

    公开(公告)日：2023-04-27

    申请号：US17983213

    申请日：2022-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Alan J. Wilson ,  Donald M. Morgan

    IPC: G06F3/06 ,  G06F12/10

    Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

    Address obfuscation for memory
    23.
    发明授权
    Address obfuscation for memory 有权

    公开(公告)号：US11042490B2

    公开(公告)日：2021-06-22

    申请号：US16192068

    申请日：2018-11-15

    Applicant: Micron Technology, Inc.

    Inventor： Donald M. Morgan ,  Sean S. Eilert ,  Bryce D. Cook

    IPC: G06F12/14 ,  G06F12/02

    Abstract: Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.

    APPARATUSES AND METHODS FOR TRACKING ROW ACCESSES
    24.
    发明申请
    APPARATUSES AND METHODS FOR TRACKING ROW ACCESSES 有权

    公开(公告)号：US20210020223A1

    公开(公告)日：2021-01-21

    申请号：US16513400

    申请日：2019-07-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

    IPC: G11C11/406 ,  G11C11/16 ,  G11C16/34 ,  G06F9/30

    Abstract: Apparatuses and methods for tracking all row accesses in a memory device over time may be used to identify rows which are being hammered so that ‘victim’ rows may be identified and refreshed. A register stack may include a number of count values, each of which may track a number of accesses to a portion of the word lines of the memory device. Anytime a row within a given portion is accessed, the associated count value may be incremented. When a count value exceeds a first threshold, a second stack with a second number of count values may be used to track numbers of accesses to sub-portions of the given portion. When a second count value exceeds a second threshold, victim addresses may be provided to refresh the victim word lines associated with any of the word lines within the sub-portion.

    Repair of memory devices using volatile and non-volatile memory
    27.
    发明授权
    Repair of memory devices using volatile and non-volatile memory 有权
    使用易失性和非易失性存储器修复存储器件

    公开(公告)号：US09349491B1

    公开(公告)日：2016-05-24

    申请号：US14690150

    申请日：2015-04-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Donald M. Morgan ,  Sujeet Ayyapureddi

    IPC: G11C17/16 ,  G11C29/00

    CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C29/78 ,  G11C29/787 ,  G11C29/88

    Abstract: Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.

    Abstract translation: 公开了用于混合后包装修复的装置和方法。 一种这样的装置可以包括包括存储器单元和易失性存储器的封装。 易失性存储器可以被配置为存储对应于被认为是有缺陷的后封装的存储器单元的第一部分的有缺陷的地址数据。 该装置还可以包括解码器，其被配置为当与要访问的地址相对应的当前地址数据与存储在易失性存储器中的缺陷地址数据匹配时，选择存储器单元的第二部分而不是存储器单元的第一部分。 该装置还可以包括包装中的非易失性存储器。 该装置还可以包括封装中的映射逻辑电路。 映射逻辑电路可以被配置为在故障地址数据被存储到易失性存储器之后将替换地址数据编程到非易失性存储器。

    Apparatuses and methods for controlling a clock signal provided to a clock tree
    28.
    发明授权
    Apparatuses and methods for controlling a clock signal provided to a clock tree 有权
    用于控制提供给时钟树的时钟信号的装置和方法

    公开(公告)号：US09087570B2

    公开(公告)日：2015-07-21

    申请号：US13744177

    申请日：2013-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P Wright

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

    Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

    Abstract translation: 描述了用于控制时钟树的时钟信号的装置，感测电路和方法。 一种示例性装置包括一个连续的写入命令检测电路，其被配置为响应于在写入命令寄存器的输出处提供的当前写入命令来检测在当前写入命令的连续写入命令周期内是否接收到下一个写入命令。 该示例设备还包括一个时钟信号控制电路，该时钟信号控制电路耦合到该连续的写命令检测电路，并且被配置为基于该连续的写入命令检测电路是否检测到下一个写入来控制到输入/输出（I / O） 命令在连续写入命令周期内。

    APPARATUSES AND METHODS FOR ERROR CORRECTION
    29.
    发明申请
    APPARATUSES AND METHODS FOR ERROR CORRECTION 有权
    用于错误校正的装置和方法

    公开(公告)号：US20140372830A1

    公开(公告)日：2014-12-18

    申请号：US13917431

    申请日：2013-06-13

    Applicant: Micron Technology, Inc.

    Inventor： Donald M. Morgan

    IPC: G06F11/10

    CPC classification number: G06F11/10

    Abstract: This disclosure relates to error correction circuitry. In one aspect, an error correction circuit can serially receive a digit stream and parse the digit stream into substrings of a predetermined length of digits. Each of the substrings can include data digits and parity digits in certain embodiments. As the substring is received, parity can be tracked in defined regions of the substring. When the entire sub string has been received, an error in one of the data digits of the sub string can be corrected based on an indication of parity in at least one defined region in some embodiments. Then corrected data, which can include the corrected data digit and the other data digits of the substring, can be stored. According to certain embodiments, the error correction circuit can be implemented by asynchronous circuitry.

    Abstract translation: 本发明涉及纠错电路。 在一个方面，纠错电路可以串行地接收数字流并将数字流解析成预定长度的数字的子串。 在某些实施例中，每个子串可以包括数据位和奇数位。 在接收到子字符串时，可以在子字符串的定义区域中跟踪奇偶校验。 当已经接收到整个子串时，在一些实施例中，可以基于在至少一个限定区域中的奇偶校验的指示来校正子串的数据位之一中的错误。 然后可以存储可以包括校正数据数字和子串的其他数据位的校正数据。 根据某些实施例，纠错电路可以由异步电路来实现。

    APPARATUSES AND METHODS FOR CONTROLLING A CLOCK SIGNAL PROVIDED TO A CLOCK TREE
    30.
    发明申请
    APPARATUSES AND METHODS FOR CONTROLLING A CLOCK SIGNAL PROVIDED TO A CLOCK TREE 有权
    用于控制提供给时钟树的时钟信号的装置和方法

    公开(公告)号：US20140198591A1

    公开(公告)日：2014-07-17

    申请号：US13744177

    申请日：2013-01-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P. Wright

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

    Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

    Abstract translation: 描述了用于控制时钟树的时钟信号的装置，感测电路和方法。 一种示例性装置包括一个连续的写入命令检测电路，其被配置为响应于在写入命令寄存器的输出处提供的当前写入命令来检测在当前写入命令的连续写入命令周期内是否接收到下一个写入命令。 该示例设备还包括一个时钟信号控制电路，该时钟信号控制电路耦合到该连续的写命令检测电路，并且被配置为基于该连续的写入命令检测电路是否检测到下一个写入来控制到输入/输出（I / O） 命令在连续写入命令周期内。

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