公开(公告)号：US11450693B2

公开(公告)日：2022-09-20

申请号：US17035856

申请日：2020-09-29

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Si-Woo Lee

IPC: H01L27/12 ,  H01L21/223 ,  H01L21/02

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have epitaxially grow single crystal silicon to fill the first horizontal opening and house a first source/drain in electrical contact with a conductive material and to form part of an integral, horizontally oriented, conductive digit line. The memory cells also have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain region. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric.

公开(公告)号：US20220130834A1

公开(公告)日：2022-04-28

申请号：US17079612

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L25/065 ,  G11C11/402

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

公开(公告)号：US11257821B1

公开(公告)日：2022-02-22

申请号：US16943494

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3205

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric.

公开(公告)号：US11164872B1

公开(公告)日：2021-11-02

申请号：US16943163

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Litao Yang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L27/108 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/265

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. An underbody conductive contact of a vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric.

公开(公告)号：US20210057418A1

公开(公告)日：2021-02-25

申请号：US16543799

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  G11C5/06

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20200258887A1

公开(公告)日：2020-08-13

申请号：US16862122

申请日：2020-04-29

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/167

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US20200227417A1

公开(公告)日：2020-07-16

申请号：US16248534

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/167 ,  H01L29/10

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US10714167B2

公开(公告)日：2020-07-14

申请号：US16431500

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/4097 ,  G11C11/22 ,  G11C5/02 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H01L27/108

Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

公开(公告)号：US20200176564A1

公开(公告)日：2020-06-04

申请号：US16209495

申请日：2018-12-04

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Yunfei Gao ,  Srinivas Pulugurtha

IPC: H01L29/08 ,  H01L27/108 ,  H01L27/088 ,  H01L21/8234

Abstract: An example apparatus includes a first transistor and a second transistor, each having asymmetric source/drain regions. A source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor at a junction. A depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor.

公开(公告)号：US10586586B1

公开(公告)日：2020-03-10

申请号：US16183594

申请日：2018-11-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyuseok Lee ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C7/06 ,  G11C11/408

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes isolation transistors, equalization transistors and precharge transistors that are used to provide threshold voltage compensation.