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    VERTICAL CONTACTS FOR SEMICONDUCTOR DEVICES
    2.
    发明申请
    VERTICAL CONTACTS FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220285365A1

    公开(公告)日：2022-09-08

    申请号：US17189485

    申请日：2021-03-02

    Applicant: Micron Technology, Inc.

    Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

    IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

    Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

    Integrated Assemblies and Semiconductor Memory Devices
    3.
    发明申请
    Integrated Assemblies and Semiconductor Memory Devices 有权

    公开(公告)号：US20220231029A1

    公开(公告)日：2022-07-21

    申请号：US17150020

    申请日：2021-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Sangmin Hwang ,  Kyuseok Lee ,  Christopher G. Wieduwilt

    IPC: H01L27/108 ,  H01L27/092 ,  G11C5/06 ,  G11C11/4091 ,  G11C11/408 ,  H01L29/78

    Abstract: Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.

    MEMORY SUBWORD DRIVER CIRCUITS AND LAYOUT
    4.
    发明申请
    MEMORY SUBWORD DRIVER CIRCUITS AND LAYOUT 有权

    公开(公告)号：US20220093158A1

    公开(公告)日：2022-03-24

    申请号：US17028929

    申请日：2020-09-22

    Applicant: Micron Technology, Inc.

    Inventor： Kyuseok Lee

    IPC: G11C11/408

    Abstract: In some examples, a subword driver block of a memory device includes a first active region and a second active region adjacent to each other. The first active region forms drains/sources of a first and second transistors in a first region; the second active region forms drains/sources of a third and fourth transistors in a second region, where the first and second regions are adjacent to each other. The first, second, third and fourth transistors are coupled to a common non-active potential via a shared contact overlaid over a merged region between the first and second regions. The first and second active regions may comprise N+ diffusion materials.

    Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same
    5.
    发明授权
    Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same 有权

    公开(公告)号：US10943644B1

    公开(公告)日：2021-03-09

    申请号：US16795293

    申请日：2020-02-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kyuseok Lee

    IPC: G11C11/40 ,  G11C11/4091 ,  G11C7/12 ,  G11C7/06 ,  G11C5/14

    Abstract: Apparatuses and methods including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example apparatus includes first and second pull-up transistors coupled to a first power supply node, and first and second pull-down transistors coupled to a second power supply node. A first isolation transistor is coupled to a gate of the second pull-down transistor and to a first sense node to which the first pull-up and first pull-down transistors are also coupled. A second isolation transistor is coupled to a gate of the first pull-down transistor and to a second sense node to which the second pull-up and second pull-down transistors are also coupled. An equalization transistor is coupled to gates of the first and second pull-down transistors, and a precharge transistor is coupled to the second power supply node and to the gate of either the first or second pull-down transistors.

    Vertical contacts for semiconductor devices
    7.
    发明授权
    Vertical contacts for semiconductor devices 有权

    公开(公告)号：US11631681B2

    公开(公告)日：2023-04-18

    申请号：US17189485

    申请日：2021-03-02

    Applicant: Micron Technology, Inc.

    Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

    IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

    Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

    Methods of forming microelectronic devices
    10.
    发明授权
    Methods of forming microelectronic devices 有权

    公开(公告)号：US10985165B2

    公开(公告)日：2021-04-20

    申请号：US16543799

    申请日：2019-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

    IPC: H01L27/108 ,  G11C5/06 ,  H01L21/768

    Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

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