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    Secure subsystem
    22.
    发明授权
    Secure subsystem 有权

    公开(公告)号：US09864879B2

    公开(公告)日：2018-01-09

    申请号：US14876600

    申请日：2015-10-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kenny T. Coker ,  David A. Pohm ,  Stephen P. Van Aken ,  Michael B. Danielson

    IPC: H04L29/06 ,  G06F21/78 ,  G06F21/60

    CPC classification number: G06F21/78 ,  G06F21/60 ,  G06F21/602 ,  G06F21/72 ,  G06F21/76

    Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

    BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM
    23.
    发明申请
    BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM 审中-公开
    多层次系统中的双工操作和设备

    公开(公告)号：US20160269147A1

    公开(公告)日：2016-09-15

    申请号：US15160322

    申请日：2016-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Bruce A. Liikanen ,  Stephen P. Van Aken ,  Gerald L. Cadloni ,  John L. Seabury ,  Robert B. Eisenhuth

    IPC: H04L1/00 ,  H03M13/35

    CPC classification number: H04L1/0041 ,  G06F11/1072 ,  H03M13/253 ,  H03M13/2936 ,  H03M13/353 ,  H04L63/0428

    Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.

    Abstract translation: 系统使用多级编码，其中多个符号的每个符号表示用于使用多级传输信道进行传送的用户数据符号流中的多于一位的信息。 以数字逐位形式表示用户数据符号，使得每个符号被呈现为多个位，并且每个位受到不同的误差概率。 基于与多个中的每个位相关联的不同误差概率应用纠错过程。 通道可被配置为支持马赛克瓦片结构，每个瓦片包含通道符号，使得所选择的瓦片具有与其他瓦片不同的集体误差概率。 可以将定制编码应用于瓦片结构，以基于总体可用校正功率将所选量的误差校正功率分配给所选择的瓦片。

    CONTROL ARRANGEMENTS AND METHODS FOR ACCESSING BLOCK ORIENTED NONVOLATILE MEMORY
    24.
    发明申请
    CONTROL ARRANGEMENTS AND METHODS FOR ACCESSING BLOCK ORIENTED NONVOLATILE MEMORY 有权
    用于访问面向对象非易失性存储器的控制装置和方法

    公开(公告)号：US20150254178A1

    公开(公告)日：2015-09-10

    申请号：US14721841

    申请日：2015-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Stephen P. Van Aken

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/1028 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7206 ,  G06F2212/7207 ,  G06F2212/7211 ,  Y02D10/13

    Abstract: A read/write arrangement is described for use in accessing at least one nonvolatile memory device in read/write operations with the memory device being made up of a plurality of memory cells which memory cells are organized as a set of pages that are physically and sequentially addressable with each page having a page length such that a page boundary is defined between successive ones of the pages in the set. The read/write arrangement includes a control arrangement that is configured to store and access a group of data blocks that is associated with a given write operation in a successive series of pages of the memory such that at least an initial page in the series is filled and each block includes a block length that is different than the page length.

    Abstract translation: 描述了用于在读/写操作中访问至少一个非易失性存储器件的读/写布置，其中存储器件由多个存储器单元构成，这些存储器单元被组织为物理和顺序的一组页 可寻址，每个页面具有页面长度，使得页面边界在集合中的连续的页面之间被定义。 读/写布置包括控制装置，其被配置为存储和访问与存储器的连续一系列页面中的给定写入操作相关联的一组数据块，使得该系列中的至少初始页面被填充 并且每个块包括与页长度不同的块长度。

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