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    Explicit skew interface for reducing crosstalk and simultaneous switching noise
    21.
    发明授权
    Explicit skew interface for reducing crosstalk and simultaneous switching noise 有权
    显式偏移接口，用于减少串扰和同时开关噪声

    公开(公告)号：US08595542B2

    公开(公告)日：2013-11-26

    申请号：US13708583

    申请日：2012-12-07

    Applicant: Micron Technology, Inc.

    Inventor： Dragos Dimitriu ,  Timothy Hollis

    IPC: G06F1/00 ,  H04J1/12 ,  H04J3/10

    CPC classification number: H04L7/04 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.

    Abstract translation: 公开了诸如涉及被配置为接收和处理电子数据的芯片间接口的方法和装置。 一个这样的接口包括接收机电路，其包括配置成在时钟树输入处接收时钟信号的时钟树。 时钟树分配从时钟信号延迟的多个时钟信号，使得一个或多个时钟信号具有与其它时钟信号的延迟不同的延迟。 接收机电路还包括多个数据输入锁存器，其被配置为在两个或多个不同的时间点上接收多个数据元素。 该配置至少部分地减少串扰和同时切换输出噪声。

    SYSTEMS AND METHODS FOR LOWERING INTERCONNECT CAPACITANCE
    22.
    发明申请
    SYSTEMS AND METHODS FOR LOWERING INTERCONNECT CAPACITANCE 有权
    降低互连电容的系统和方法

    公开(公告)号：US20130069705A1

    公开(公告)日：2013-03-21

    申请号：US13674535

    申请日：2012-11-12

    Applicant: Micron Technology, Inc.

    Inventor： Timothy Hollis

    IPC: H03L5/00

    CPC classification number: H01L23/481 ,  H01L23/50 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/14 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    Abstract: Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to pass a signal through at least a portion of the at least one integrated circuit. The apparatus may include a transmitter to operate at a first voltage and a second voltage, and to output to an end node of the interconnect a reduced swing signal ranging from the first voltage to a third voltage. The third voltage may be between the first and second voltages, and the reduced swing signal may operate to reduce a capacitance of the interconnect when compared to operating the transmitter at the second voltage. Additional apparatus and methods are disclosed.

    Abstract translation: 公开了用于降低互连电容的方法和装置。 示例性设备可以包括形成在至少一个集成电路中并被配置为使信号通过至少一个集成电路的至少一部分的互连。 该装置可以包括在第一电压和第二电压下操作的发射器，并且向互连的端节点输出从第一电压到第三电压的减小的摆动信号。 第三电压可以在第一和第二电压之间，并且与在第二电压下操作发射机相比，减小的摆动信号可以操作以减小互连的电容。 公开了附加的装置和方法。

    MULTI-COIL INDUCTION APPARATUS
    23.
    发明公开
    MULTI-COIL INDUCTION APPARATUS 审中-公开

    公开(公告)号：US20230395317A1

    公开(公告)日：2023-12-07

    申请号：US18203735

    申请日：2023-05-31

    Applicant: Micron Technology, Inc.

    Inventor： Timothy Hollis ,  David Ovard

    IPC: H01F27/40 ,  H01F27/30

    CPC classification number: H01F27/402 ,  H01F27/306

    Abstract: Systems, methods and apparatus are provided for a multi-coil induction apparatus. The multi-coil induction apparatus has a primary coil structure with a primary first coil portion and a primary second coil portion where both are on a common planar surface; and a secondary coil structure having a secondary first coil portion and a secondary second coil, where the secondary first coil portion and the secondary second coil portion are coplanar with the primary first coil portion and the primary second coil. The primary first coil portion and the secondary first coil portion concentrically turn on the common planar surface to form a coupled induction section while the primary second coil portion and the secondary second coil portion are adjacent the coupled induction section on the common planar surface.

    Reference voltage generator for single-ended communication systems
    27.
    发明授权
    Reference voltage generator for single-ended communication systems 有权
    单端通信系统的参考电压发生器

    公开(公告)号：US08891685B2

    公开(公告)日：2014-11-18

    申请号：US14053200

    申请日：2013-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Timothy Hollis

    IPC: H04L25/06 ,  G11C5/14 ,  G06F13/00

    CPC classification number: H03K5/2472 ,  G06F13/00 ,  G06F13/4072 ,  G11C5/14 ,  H04B1/16 ,  H04L25/06

    Abstract: In various embodiments, a reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (e.g., Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply.

    Abstract translation: 在各种实施例中，公开了一种用于通信系统中的单端接收机的参考电压（Vref）发生器。 一个示例中的Vref发生器包括用于向电阻器Rb提供电流I以产生Vref电压（I * Rb）的级联电流源。 因为电流源将Vref与两个电源中的第一个隔离，所以Vref将仅随耦合到Rb的第二个电源而变化。 因此，Vref发生器在使用参考该第二电源但具有解耦第一电源的信号的系统中是有用的。 例如，在其中第二电源（例如，Vssq）对于两个装置是公共的但是第一电源（Vddq）不是）的通信系统中，所公开的Vref发生器产生用于跟踪Vssq而不是第一电源 。

    EXPLICIT SKEW INTERFACE FOR REDUCING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE
    28.
    发明申请
    EXPLICIT SKEW INTERFACE FOR REDUCING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE 有权
    用于减少摇滚音箱和同时开关噪音的显示切口界面

    公开(公告)号：US20130094615A1

    公开(公告)日：2013-04-18

    申请号：US13708583

    申请日：2012-12-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dragos Dimitriu ,  Timothy Hollis

    IPC: H04L7/04

    CPC classification number: H04L7/04 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.

    Abstract translation: 公开了诸如涉及被配置为接收和处理电子数据的芯片间接口的方法和装置。 一个这样的接口包括接收机电路，其包括配置成在时钟树输入处接收时钟信号的时钟树。 时钟树分配从时钟信号延迟的多个时钟信号，使得一个或多个时钟信号具有与其它时钟信号的延迟不同的延迟。 接收机电路还包括多个数据输入锁存器，其被配置为在两个或多个不同的时间点上接收多个数据元素。 该配置至少部分地减少串扰和同时切换输出噪声。

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