公开(公告)号：US09940097B1

公开(公告)日：2018-04-10

申请号：US14527550

申请日：2014-10-29

Applicant: Netronome Systems, Inc.

Inventor： Ronald N. Fortino ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F3/00 ,  G06F5/00 ,  G06F5/14 ,  H04L25/00 ,  G06F13/40 ,  G06F9/34 ,  H04B1/38

CPC classification number: G06F5/14 ,  G06F5/08 ,  G06F9/34 ,  G06F13/40 ,  G06F2205/126 ,  H04B1/38 ,  H04L25/00

Abstract: A registered synchronous FIFO has a tail register, internal registers, and a head register. The FIFO cannot be pushed if it is full and cannot be popped if it is empty, but otherwise can be pushed and/or popped. Within the FIFO, the internal signal fanout of incoming data circuitry and push control circuitry and is minimized and remains essentially constant regardless of the number of registers of the FIFO. The output delay of the output data also is essentially constant regardless of the number of registers of the FIFO. An incoming data value can only be written into the head or tail. If a data value is in the tail and one of the internal registers is empty, and if no push or pop is to be performed in a clock cycle, then nevertheless the data value in the tail is moved into the empty internal register in the cycle.

公开(公告)号：US09804959B2

公开(公告)日：2017-10-31

申请号：US14530599

申请日：2014-10-31

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Steven W. Zagorianakos ,  Gavin J. Stark

IPC: G06F9/46 ,  G06F15/173 ,  G06F12/02 ,  H04L29/06

CPC classification number: G06F12/023 ,  G06F12/0223 ,  G06F2212/174 ,  G06F2212/254 ,  H04L69/22

Abstract: A method for supporting in-flight packet processing is provided. Packet processing devices (microengines) can send a request for packet processing to a packet engine before a packet comes in. The request offers a twofold benefit. First, the microengines add themselves to a work queue to request for processing. Once the packet becomes available, the header portion is automatically provided to the corresponding microengine for packet processing. Only one bus transaction is involved in order for the microengines to start packet processing. Second, the microengines can process packets before the entire packet is written into the memory. This is especially useful for large sized packets because the packets do not have to be written into the memory completely when processed by the microengines.

公开(公告)号：US09401880B1

公开(公告)日：2016-07-26

申请号：US14588084

申请日：2014-12-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber ,  Richard P. Bouley

IPC: H04L12/54 ,  G06F15/80 ,  H04L12/861 ,  H04L12/933 ,  H04L12/801

CPC classification number: H04L49/9047 ,  H04L47/13 ,  H04L49/102 ,  H04L49/9084

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.

公开(公告)号：US20150277924A1

公开(公告)日：2015-10-01

申请号：US14231028

申请日：2014-03-31

Applicant: Netronome Systems, Inc.

Inventor： Frank J. Zappulla ,  Steven W. Zagorianakos ,  Rajesh Vaidheeswarran

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3836 ,  G06F9/3877 ,  G06F9/46 ,  G06F9/4881 ,  G06F21/00 ,  G06F21/72

Abstract: A dispatcher circuit receives sets of instructions from an instructing entity. Instructions of the set of a first type are put into a first queue circuit, instructions of the set of a second type are put into a second queue circuit, and so forth. The first queue circuit dispatches instructions of the first type to one or more processing engines and records when the instructions of the set are completed. When all the instructions of the set of the first type have been completed, then the first queue circuit sends the second queue circuit a go signal, which causes the second queue circuit to dispatch instructions of the second type and to record when they have been completed. This process proceeds from queue circuit to queue circuit. When all the instructions of the set have been completed, then the dispatcher circuit returns an “instructions done” to the original instructing entity.

Abstract translation: 调度器电路从指导实体接收指令集。 将第一类型的集合的指令放入第一队列电路中，将第二类型的集合的指令放入第二队列电路中，等等。 第一个队列电路将第一类型的指令分配给一个或多个处理引擎，并且当该组的指令完成时记录。 当所述第一类型的所有指令已经完成时，第一队列电路向第二队列电路发送去信号，这使得第二队列电路调度第二类型的指令并记录它们何时完成 。 该过程从队列电路进行到队列电路。 当集合的所有指令已经完成时，调度器电路向原始指令实体返回“完成指令”。

公开(公告)号：US20150193484A1

公开(公告)日：2015-07-09

申请号：US14151666

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F17/30

CPC classification number: H04L12/6418 ,  G06F9/4498 ,  G06F17/30283 ,  G11C15/00

Abstract: An automaton hardware engine employs a transition table organized into 2n rows, where each row comprises a plurality of n-bit storage locations, and where each storage location can store at most one n-bit entry value. Each row corresponds to an automaton state. In one example, at least two NFAs are encoded into the table. The first NFA is indexed into the rows of the transition table in a first way, and the second NFA is indexed in to the rows of the transition table in a second way. Due to this indexing, all rows are usable to store entry values that point to other rows.

Abstract translation: 自动机硬件引擎采用组织成2n行的转换表，其中每行包括多个n位存储位置，并且其中每个存储位置最多可以存储一个n位输入值。 每行对应于自动机状态。 在一个示例中，至少两个NFA被编码到表中。 第一个NFA以第一种方式索引到转换表的行中，第二个NFA以第二种方式索引到转换表的行中。 由于此索引，所有行都可用于存储指向其他行的条目值。

公开(公告)号：US20150193374A1

公开(公告)日：2015-07-09

申请号：US14151688

申请日：2014-01-09

Applicant: NETRONOME SYSTEMS, INC.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F15/167 ,  G06F1/10

CPC classification number: G06F1/10 ,  G06F9/4498 ,  G06F12/00 ,  G06F13/00 ,  H04L45/7457 ,  H04L67/00

Abstract: An automaton hardware engine employs a transition table organized into 2n rows, where each row comprises a plurality of n-bit storage locations, and where each storage location can store at most one n-bit entry value. Each row corresponds to an automaton state. In one example, at least two NFAs are encoded into the table. The first NFA is indexed into the rows of the transition table in a first way, and the second NFA is indexed in to the rows of the transition table in a second way. Due to this indexing, all rows are usable to store entry values that point to other rows.

Abstract translation: 自动机硬件引擎采用组织成2n行的转换表，其中每行包括多个n位存储位置，并且其中每个存储位置最多可以存储一个n位输入值。 每行对应于自动机状态。 在一个示例中，至少两个NFA被编码到表中。 第一个NFA以第一种方式索引到转换表的行中，第二个NFA以第二种方式索引到转换表的行中。 由于此索引，所有行都可用于存储指向其他行的条目值。