公开(公告)号：US20200051314A1

公开(公告)日：2020-02-13

申请号：US16101148

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Samuli Laine ,  Tero Karras ,  Timo Aila ,  Robert Ohannessian ,  William Parsons Newhall, JR. ,  Greg Muthler ,  Ian Kwong ,  Peter Nelson ,  John Burgess

IPC: G06T15/06 ,  G06T17/00 ,  G06T15/00

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.

公开(公告)号：US10241798B2

公开(公告)日：2019-03-26

申请号：US14033378

申请日：2013-09-20

Applicant: NVIDIA CORPORATION

Inventor： Peter Sommers ,  Peter Nelson ,  Aniket Naik ,  John H. Edmondson

IPC: G06F9/38

Abstract: An issue control unit is configured to control the rate at which an instruction issue unit issues instructions to an execution pipeline in order to avoid spikes in power drawn by that execution pipeline. The issue control unit maintains a history buffer that reflects, for N previous cycles, the number of instructions issued during each of those N cycles. If the total number of instructions issued during the N previous cycles exceeds a threshold value, then the issue control unit throttles the instruction issue unit from issuing instructions during a subsequent cycle. In addition, the issue control unit increases the threshold value in proportion to the number of previously issued instructions and based on a variety of configurable parameters. Accordingly, the issue control unit maintains granular control over the rate with which the instruction issue unit “ramps up” to a maximum instruction issue rate.

公开(公告)号：US10067768B2

公开(公告)日：2018-09-04

申请号：US14798265

申请日：2015-07-13

Applicant: NVIDIA Corporation

Inventor： Gregory Frederick Diamos ,  Richard Craig Johnson ,  Vinod Grover ,  Olivier Giroux ,  Jack H. Choquette ,  Michael Alan Fetterman ,  Ajay S. Tirumala ,  Peter Nelson ,  Ronny Meir Krashinsky

IPC: G06F9/38 ,  G06F9/52 ,  G06F9/30

Abstract: A method, system, and computer program product for executing divergent threads using a convergence barrier are disclosed. A first instruction in a program is executed by a plurality of threads, where the first instruction, when executed by a particular thread, indicates to a scheduler unit that the thread participates in a convergence barrier. A first path through the program is executed by a first divergent portion of the participating threads and a second path through the program is executed by a second divergent portion of the participating threads. The first divergent portion of the participating threads executes a second instruction in the program and transitions to a blocked state at the convergence barrier. The scheduler unit determines that all of the participating threads are synchronized at the convergence barrier and the convergence barrier is cleared.

公开(公告)号：US09836878B2

公开(公告)日：2017-12-05

申请号：US14820438

申请日：2015-08-06

Applicant: NVIDIA Corporation

Inventor： Ziyad Sami Hakura ,  Peter Nelson

IPC: G06T15/80 ,  G06T15/87 ,  G06T15/00

CPC classification number: G06T15/87 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A system, method, and computer program product are provided for processing primitive-specific attributes. A portion of a graphics processor is determined to operate in a fast geometry shader mode and a vertex associated with a set of per-vertex attributes is determined to be a shared vertex. The shared vertex is determined to be a non-provoking vertex corresponding to a first primitive that is associated with a first set of per-primitive attributes and the shared vertex is determined to be a provoking vertex corresponding to a second primitive that is associated with a second set of per-primitive attributes. Only one set of the per-vertex attributes associated with the shared vertex is stored and only one of the second set of per-primitive attributes associated with the second primitive is stored.

公开(公告)号：US20160019066A1

公开(公告)日：2016-01-21

申请号：US14798265

申请日：2015-07-13

Applicant: NVIDIA CORPORATION

Inventor： Gregory Frederick Diamos ,  Richard Craig Johnson ,  Vinod Grover ,  Olivier Giroux ,  Jack H. Choquette ,  Michael Alan Fetterman ,  Ajay S. Tirumala ,  Peter Nelson ,  Ronny Meir Krashinsky

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/522 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3887

Abstract: A method, system, and computer program product for executing divergent threads using a convergence barrier are disclosed. A first instruction in a program is executed by a plurality of threads, where the first instruction, when executed by a particular thread, indicates to a scheduler unit that the thread participates in a convergence barrier. A first path through the program is executed by a first divergent portion of the participating threads and a second path through the program is executed by a second divergent portion of the participating threads. The first divergent portion of the participating threads executes a second instruction in the program and transitions to a blocked state at the convergence barrier. The scheduler unit determines that all of the participating threads are synchronized at the convergence barrier and the convergence barrier is cleared.

Abstract translation: 公开了一种使用会聚障碍来执行发散线程的方法，系统和计算机程序产品。 程序中的第一指令由多个线程执行，其中当特定线程执行时，第一指令向调度器单元指示线程参与会聚障碍。 通过程序的第一路径由参与线程的第一发散部分执行，并且通过程序的第二路径由参与线程的第二发散部分执行。 参与线程的第一发散部分执行程序中的第二条指令，并在会聚障碍处转变为阻塞状态。 调度器单元确定所有参与线程在会聚障碍处被同步，并且会聚障碍被清除。

公开(公告)号：US20150348317A1

公开(公告)日：2015-12-03

申请号：US14820438

申请日：2015-08-06

Applicant: NVIDIA Corporation

Inventor： Ziyad Sami Hakura ,  Peter Nelson

IPC: G06T15/87 ,  G06T15/00

CPC classification number: G06T15/87 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A system, method, and computer program product are provided for processing primitive-specific attributes. A portion of a graphics processor is determined to operate in a fast geometry shader mode and a vertex associated with a set of per-vertex attributes is determined to be a shared vertex. The shared vertex is determined to be a non-provoking vertex corresponding to a first primitive that is associated with a first set of per-primitive attributes and the shared vertex is determined to be a provoking vertex corresponding to a second primitive that is associated with a second set of per-primitive attributes. Only one set of the per-vertex attributes associated with the shared vertex is stored and only one of the second set of per-primitive attributes associated with the second primitive is stored.

Abstract translation: 提供了一种用于处理原始特定属性的系统，方法和计算机程序产品。 图形处理器的一部分被确定为以快速几何着色器模式操作，并且与一组每顶点属性相关联的顶点被确定为共享顶点。 共享顶点被确定为对应于与第一组每个原始属性相关联的第一原语的非启发性顶点，并且共享顶点被确定为与第二原语相关联的第二原语对应的激发顶点 第二组每个原始属性。 仅存储与共享顶点相关联的一组每顶点属性，并且仅存储与第二原语相关联的第二组每个基元属性中的一个。