公开(公告)号：US11487341B2

公开(公告)日：2022-11-01

申请号：US16460615

申请日：2019-07-02

Applicant: NVIDIA Corporation

Inventor： Aniket Naik ,  Tezaswi Raja ,  Kevin Wilder ,  Rajeshwaran Selvanesan ,  Divya Ramakrishnan ,  Daniel Rodriguez ,  Benjamin Faulkner ,  Raj Jayakar ,  Fei (Walter) Li

IPC: G06F1/324 ,  G06F9/38

Abstract: Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.

公开(公告)号：US11106261B2

公开(公告)日：2021-08-31

申请号：US16179620

申请日：2018-11-02

Applicant: NVIDIA Corporation

Inventor： Aniket Naik ,  Siddharth Bhargav ,  Bardia Zandian ,  Narayan Kulshrestha ,  Amit Pabalkar ,  Arvind Gopalakrishnan ,  Justin Tai ,  Sachin Satish Idgunji

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/3206 ,  G06F9/50 ,  G06F1/3296 ,  G06F1/28 ,  G06N20/00 ,  G06N5/04

Abstract: Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.

公开(公告)号：US10241798B2

公开(公告)日：2019-03-26

申请号：US14033378

申请日：2013-09-20

Applicant: NVIDIA CORPORATION

Inventor： Peter Sommers ,  Peter Nelson ,  Aniket Naik ,  John H. Edmondson

IPC: G06F9/38

Abstract: An issue control unit is configured to control the rate at which an instruction issue unit issues instructions to an execution pipeline in order to avoid spikes in power drawn by that execution pipeline. The issue control unit maintains a history buffer that reflects, for N previous cycles, the number of instructions issued during each of those N cycles. If the total number of instructions issued during the N previous cycles exceeds a threshold value, then the issue control unit throttles the instruction issue unit from issuing instructions during a subsequent cycle. In addition, the issue control unit increases the threshold value in proportion to the number of previously issued instructions and based on a variety of configurable parameters. Accordingly, the issue control unit maintains granular control over the rate with which the instruction issue unit “ramps up” to a maximum instruction issue rate.