-
公开(公告)号：US20140152353A1
公开(公告)日：2014-06-05
申请号：US14172256
申请日：2014-02-04
Applicant: NXP B.V.
Inventor： Mustafa Acar , Katarzyna Nowak
IPC: H03K19/0185
CPC classification number: H03K19/018521 , H03K19/00315 , H03K19/018528
Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.
Abstract translation: 功率级具有由一个或多个缓冲级4驱动的差分输出级2.缓冲级4被实现为高侧缓冲器12和低侧缓冲器12,14，每个缓冲器本身都是使用形成在隔离级中的晶体管实现的差分缓冲器， 良好的技术，如三阱CMOS。
-
公开(公告)号：US12155127B2
公开(公告)日：2024-11-26
申请号：US18051941
申请日：2022-11-02
Applicant: NXP B.V.
Inventor： Lucas Maria Florentinus De Maaijer , Mustafa Acar , Paul Mattheijssen
Abstract: A multiple-input multiple-output (MIMO) antenna system for a mobile cellular network and method is described. The MIMO antenna system includes an array of dual-polarization patch antennas each having first and second polarization feed-points, a first polarization radio chain and a second polarization radio chain. The MIMO antenna system includes a beamformer coupled to the first and second polarization radio chains. The beamformer includes a beamformer channel for a respective feedpoint and further includes a transmit amplifier and a detector (coupler) coupled to a transmit amplifier output. In one mode of operation, a signal is transmitted via the first polarization feed-point of a dual-polarisation patch antennas and a replica of the transmitted signal may be sensed using the coupler at the output of the transmit amplifier and routed via the second polarization radio chain to a digital predistortion module. The digital pre-distortion module is configured to digitally pre-distort a signal for transmission dependent on the replica of the RF signal.
-
公开(公告)号：US20240138129A1
公开(公告)日：2024-04-25
申请号：US18048495
申请日：2022-10-20
Applicant: NXP B.V.
Inventor： Philipp Franz Freidl , Mustafa Acar , Antonius Hendrikus Jozef Kamphuis , Erik Daniel Björk , Konstantinos Giannakidis , Jan Willem Bergman , Rajesh Mandamparambil , Paul Mattheijssen
IPC: H05K9/00 , H01L23/552
CPC classification number: H05K9/0032 , H01L23/552 , H05K9/0088
Abstract: One example discloses an on-chip shielded device, including: a planar structure including a substrate and a passivation layer; an electrical component formed within the substrate and coupled to an input signal path and an output signal path; a first shielding element positioned above the electrical component and the passivation layer; and a second shielding element positioned above the electrical component, the passivation layer and the first shielding element.
-
公开(公告)号：US20230361443A1
公开(公告)日：2023-11-09
申请号：US17662572
申请日：2022-05-09
Applicant: NXP B.V.
Inventor： Mustafa Acar , Danny Wayling Chang , Dominicus Martinus Wilhelmus Leenaerts , Philipp Franz Freidl
Abstract: A transmission line includes a signal conductor and one or more return conductors, one or more of which having a stepped multi-layer structure. The return conductors may be disposed at opposite sides of the signal conductor. The return conductors may be multi-layer structures. At least some layers of each return conductor may have a stepped arrangement that defines a curve, such as an exponential curve. Additionally or alternatively, the signal conductor may be a stepped multi-layer structure, where at least some layers of the signal conductor may define a curve, such as an exponential curve. The signal conductor may be disposed at one or more upper layers of the transmission line or may be embedded at one or more layers near the center of the transmission line.
-
公开(公告)号：US20220263222A1
公开(公告)日：2022-08-18
申请号：US17649725
申请日：2022-02-02
Applicant: NXP B.V.
Inventor： Antonius Hendrikus Jozef Kamphuis , Jan Willem Bergman , Marcellinus Johannes Maria Geurts , Mustafa Acar , Paul Mattheijssen , Rajesh Mandamparambil , Andrei-Alexandru Damian , Amar Ashok Mavinkurve
IPC: H01Q1/22 , H01Q9/04 , H01L25/065 , H01L23/60 , H01L25/00
Abstract: A semiconductor device comprising a substrate, a first integrated circuit package mounted on the substrate, the first integrated circuit package comprising a first antenna sub-array having a uniform pitch, and a second integrated circuit package mounted on the substrate, the second integrated circuit package comprising a second antenna sub-array having a uniform pitch. The second integrated circuit package is mounted adjacent to the first integrated circuit package to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, wherein the antenna array has a uniform pitch. Also provided is a method of manufacturing a multi-package module and a method of providing package-to-package grounding.
-
Patent Agency Ranking
公开(公告)号：US20170230106A1
公开(公告)日：2017-08-10
申请号：US15427092
申请日：2017-02-08
Applicant: NXP B.V.
Inventor： Robin Wesson , Mustafa Acar
CPC classification number: H03F1/0294 , H04L27/00
Abstract: An outphasing amplifier having: a first branch to receive and process a first branch signal, the first branch signal being phase modulated, with constant amplitude envelope; and a second branch arranged to receive and process a second branch signal, the second branch signal being phase modulated, with constant amplitude envelope, and at least a portion of the second branch signal anti-phase from the first branch signal, wherein each branch includes: circuitry arranged to process the signal to reduce the energy in sidebands of the signal away from the central frequency, while retaining the phase information in the signal; and an amplifier arranged to amplify the filtered and re-asserted branch signal.
-
公开(公告)号：US08692591B2
公开(公告)日：2014-04-08
申请号：US13661275
申请日：2012-10-26
Applicant: NXP B.V.
Inventor： Mustafa Acar , Katarzyna Nowak
IPC: H03K3/00
CPC classification number: H03K19/018521 , H03K19/00315 , H03K19/018528
Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.
Abstract translation: 功率级具有由一个或多个缓冲级4驱动的差分输出级2.缓冲级4被实现为高侧缓冲器12和低侧缓冲器12,14，每个缓冲器本身都是使用形成在隔离级中的晶体管实现的差分缓冲器， 良好的技术，如三阱CMOS。
-
公开(公告)号：US20140077877A1
公开(公告)日：2014-03-20
申请号：US14027109
申请日：2013-09-13
Applicant: NXP B.V.
Inventor： Koen Buisman , Mark Pieter van der Heijden , Mustafa Acar , Leo de Vreede
IPC: H03F3/217
CPC classification number: H03F3/2171 , H03F3/2176
Abstract: An amplifier circuit comprising a driver (204, 304) configured to provide a switched mode input signal, a switching mode power amplifier (206, 306) configured to receive the switched mode input signal and provide an output signal for an external load (210, 310); and a sensor (208, 308) configured to sense the impedance of the external load (210, 310) The driver is configured to set the duty cycle of the switched mode input signal in accordance with the sensed impedance of the external load (210, 310).
Abstract translation: 一种放大器电路，包括被配置为提供开关模式输入信号的驱动器（204,304），被配置为接收所述开关模式输入信号并提供用于外部负载的输出信号的开关模式功率放大器（206,306） 310）; 以及被配置为感测外部负载（210,310）的阻抗的传感器（208,308）。驱动器被配置为根据感测到的外部负载的阻抗来设置开关模式输入信号的占空比， 310）。
-
公开(公告)号：US20130285713A1
公开(公告)日：2013-10-31
申请号：US13661275
申请日：2012-10-26
Applicant: NXP B.V.
Inventor： Mustafa Acar , Katarzyna Nowak
IPC: H03K19/0185
CPC classification number: H03K19/018521 , H03K19/00315 , H03K19/018528
Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.
Abstract translation: 功率级具有由一个或多个缓冲级4驱动的差分输出级2.缓冲级4被实现为高侧缓冲器12和低侧缓冲器12,14，每个缓冲器本身都是使用形成在隔离级中的晶体管实现的差分缓冲器， 良好的技术，如三阱CMOS。
-
公开(公告)号：US12212074B2
公开(公告)日：2025-01-28
申请号：US17651832
申请日：2022-02-21
Applicant: NXP B.V.
Inventor： Jan Willem Bergman , Mustafa Acar , Antonius Hendrikus Jozef Kamphuis , Dominicus Martinus WilHelmus Leenaerts , Rajesh Mandamparambil , Paul Mattheijssen
Abstract: An integrated circuit comprising a package, phased antenna array and die. The die comprises a plurality of unit cells, wherein each unit cell is divided into quadrants. Each quadrant comprises a receiver terminal located on a first axis, and a transmitter terminal located on a second axis, wherein the first axis is orthogonal to the second axis, and there is mirror symmetry between the nearest neighbour quadrants in the unit cell. The package comprises a plurality of pairs of feed lines, each pair of feed lines comprising a receiver feed line and a transmitter feed line. The receiver feed line is connected to one of the receiver terminals and the transmitter feed line is connected to the transmitter terminal in the same die quadrant. The receiver feed line is orthogonal to the transmitter feed line. Each antenna element is coupled to a respective pair of feed lines.
-
-
-
-
-
-
-
-
-
Search Results
37
records
(took 0.014 seconds)
