公开(公告)号：US08168532B2

公开(公告)日：2012-05-01

申请号：US12267970

申请日：2008-11-10

申请人： Masaki Haneda ,  Michie Sunayama ,  Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Yoshiyuki Nakao ,  Takahiro Tabira

发明人： Masaki Haneda ,  Michie Sunayama ,  Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Yoshiyuki Nakao ,  Takahiro Tabira

IPC分类号： H01L21/768 ,  H01L23/538 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/2855 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.

摘要翻译： 半导体器件包括半导体衬底，设置在上述半导体衬底上方的含氧绝缘膜，设置在上述绝缘膜中的凹部，设置在上述绝缘膜的内壁上的含铜第一膜， 设置在上述第一膜上方并填充在上述凹部中的含铜第二膜和设置在上述第一膜和上述第二膜之间的含锰氧化物层 。 此外，通过电镀方法在上述结构上形成铜互连，随后在80℃至120℃的温度下进行短时热处理。

公开(公告)号：US08119524B2

公开(公告)日：2012-02-21

申请号：US12967650

申请日：2010-12-14

申请人： Michie Sunayama ,  Noriyoshi Shimizu

发明人： Michie Sunayama ,  Noriyoshi Shimizu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76883 ,  H01L2221/1089

摘要： A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film.

摘要翻译： 含有具有铜扩散防止功能的第一金属材料的第一膜，含有含氧铜膜的第二膜，含有铜的第三膜和通过与氧结合而显示铜的扩散防止功能的第二金属材料，以及 以形成在绝缘膜中的开口形成作为主要材料的第四铜的膜，然后通过绝缘膜和第四膜之间的热处理形成包含第一金属材料，第二金属材料和氧的阻挡层 。

公开(公告)号：US08003527B2

公开(公告)日：2011-08-23

申请号：US12843356

申请日：2010-07-26

申请人： Michie Sunayama ,  Noriyoshi Shimizu

发明人： Michie Sunayama ,  Noriyoshi Shimizu

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76873 ,  H01L21/2885 ,  H01L21/76229 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883

摘要： A semiconductor device manufacturing method includes forming an interlayer dielectric film above a semiconductor substrate; forming a first wiring trench with a first width and a second wiring trench with a second width that is larger than the first width inr the interlayer dielectric film; forming a first seed layer that includes a first additional element in the first wiring trench and the second wiring trench; forming a first copper layer over the first seed layer; removing the first copper layer and the first seed layer in the second wiring trench while leaving the first copper layer and the first seed layer in the first wiring trench; forming a second seed layer in the second wiring trench after removing the first copper layer and the first seed layer in the second wiring trench; and forming a second copper layer over the second seed layer.

摘要翻译： 半导体器件制造方法包括在半导体衬底上形成层间电介质膜; 形成具有第一宽度的第一布线沟槽和具有大于层间绝缘膜中的第一宽度的第二宽度的第二布线沟槽; 在所述第一布线沟槽和所述第二布线沟槽中形成包括第一附加元件的第一晶种层; 在所述第一种子层上形成第一铜层; 在第一布线沟槽中留下第一铜层和第一种子层的同时，去除第二布线沟槽中的第一铜层和第一晶种层; 在去除第二布线沟槽中的第一铜层和第一籽晶层之后，在第二布线沟槽中形成第二晶种层; 以及在所述第二晶种层上形成第二铜层。

公开(公告)号：US07994055B2

公开(公告)日：2011-08-09

申请号：US12022742

申请日：2008-01-30

申请人： Hisaya Sakai ,  Noriyoshi Shimizu

发明人： Hisaya Sakai ,  Noriyoshi Shimizu

IPC分类号： H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76873

摘要： A method of manufacturing a semiconductor apparatus which includes the steps of forming a via hole and a wire trench reaching an underlying wire in an interlayer insulation film formed on the underlying wire, forming an diffusion barrier film on said underlying wire exposed through said via hole, on an inner wall of said via hole and on an inner wall of said wire trench, forming a seed layer on said underlying wire and on said diffusion barrier film formed on the inner wall of said via hole and the inner wall of said wire trench while concurrently said diffusion barrier film deposited on the bottom of said via hole is being etched, and forming metal wire in said via hole and in said wire trench.

摘要翻译： 一种制造半导体装置的方法，包括以下步骤：在形成在下面的导线上的层间绝缘膜中形成到达下层导线的通孔和导线沟槽，在通过所述通孔暴露的所述下层导线上形成扩散阻挡膜， 在所述通孔的内壁上和所述导线沟槽的内壁上，在所述底层导线上形成种子层，以及形成在所述通孔的内壁和所述导线沟槽的内壁上的所述扩散阻挡膜上，同时 沉积在所述通孔的底部上的所述扩散阻挡膜同时被蚀刻，并且在所述通孔中和所述导线沟槽中形成金属线。

公开(公告)号：US20110034026A1

公开(公告)日：2011-02-10

申请号：US12843356

申请日：2010-07-26

申请人： Michie Sunayama ,  Noriyoshi Shimizu

发明人： Michie Sunayama ,  Noriyoshi Shimizu

IPC分类号： H01L21/768

CPC分类号： H01L21/76873 ,  H01L21/2885 ,  H01L21/76229 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883

摘要： A semiconductor device manufacturing method includes forming an interlayer dielectric film above a semiconductor substrate; forming a first wiring trench with a first width and a second wiring trench with a second width that is larger than the first width inr the interlayer dielectric film; forming a first seed layer that includes a first additional element in the first wiring trench and the second wiring trench; forming a first copper layer over the first seed layer; removing the first copper layer and the first seed layer in the second wiring trench while leaving the first copper layer and the first seed layer in the first wiring trench; forming a second seed layer in the second wiring trench after removing the first copper layer and the first seed layer in the second wiring trench; and forming a second copper layer over the second seed layer.

摘要翻译： 半导体器件制造方法包括在半导体衬底上形成层间电介质膜; 形成具有第一宽度的第一布线沟槽和具有大于层间绝缘膜中的第一宽度的第二宽度的第二布线沟槽; 在所述第一布线沟槽和所述第二布线沟槽中形成包括第一附加元件的第一晶种层; 在所述第一种子层上形成第一铜层; 在第一布线沟槽中留下第一铜层和第一种子层的同时，去除第二布线沟槽中的第一铜层和第一晶种层; 在去除第二布线沟槽中的第一铜层和第一籽晶层之后，在第二布线沟槽中形成第二晶种层; 以及在所述第二晶种层上形成第二铜层。

公开(公告)号：US20110021020A1

公开(公告)日：2011-01-27

申请号：US12895002

申请日：2010-09-30

申请人： Hisaya Sakai ,  Noriyoshi Shimizu

发明人： Hisaya Sakai ,  Noriyoshi Shimizu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation film, an interconnection trench formed in an upper part of the second insulation film, a via-hole extending downward from the interconnection trench at a lower part of the second insulation film, the via-hole exposing the first interconnection pattern, a second interconnection pattern filling the interconnection trench, a via-plug extending downward in the via-hole from the second interconnection pattern and making a contact with the first interconnection pattern, and a barrier metal film formed between the second interconnection pattern and the interconnection trench, the barrier metal film covering a surface of the via-plug continuously, wherein the via-plug has a tip end part invading into the first interconnection pattern across a surface of said first interconnection pattern, the interconnection trench has a flat bottom surface, and the barrier metal film has a larger film thickness at the tip end part of the via-plug as compared with a sidewall surface of the via-plug.

摘要翻译： 半导体器件包括嵌入第一绝缘膜中的第一互连图案，覆盖第一绝缘膜上的第一互连图案的第二绝缘膜，形成在第二绝缘膜的上部的互连沟槽，向下延伸的通孔 从所述第二绝缘膜的下部的所述互连沟槽，暴露所述第一互连图案的通孔，填充所述互连沟槽的第二互连图案，从所述第二互连图案在所述通孔中向下延伸的通孔插塞;以及 与所述第一互连图案接触，以及形成在所述第二互连图案和所述互连沟槽之间的阻挡金属膜，所述阻挡金属膜连续地覆盖所述通孔的表面，其中所述通孔插塞具有尖端部分侵入 跨越所述第一互连图案的表面的第一互连图案，互连 所述沟槽具有平坦的底面，与所述通孔的侧壁面相比，所述阻挡金属膜在所述通孔的前端部具有较大的膜厚。

公开(公告)号：US20100323519A1

公开(公告)日：2010-12-23

申请号：US12853676

申请日：2010-08-10

申请人： Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Hideki Kitada ,  Yoshiyuki Nakao

发明人： Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Hideki Kitada ,  Yoshiyuki Nakao

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.

摘要翻译： （a1）在半导体基板上形成的层间绝缘膜中形成有凹部。 （a2）通过CVD形成Mn的第一膜，所述第一膜覆盖所述凹部的内表面和所述绝缘膜的上表面。 （a3）基本上由Cu组成的导电材料沉积在第一膜上，以将导电材料嵌入凹部中。 （a4）半导体衬底退火。 在形成阻挡层的同时具有提高紧密粘合性的功能的期间，能够确保布线部件的充分的密合性，防止配线部件的剥离。

公开(公告)号：US07846833B2

公开(公告)日：2010-12-07

申请号：US12731515

申请日：2010-03-25

申请人： Hideki Kitada ,  Nobuyuki Ohtsuka ,  Noriyoshi Shimizu ,  Yoshiyuki Nakao

发明人： Hideki Kitada ,  Nobuyuki Ohtsuka ,  Noriyoshi Shimizu ,  Yoshiyuki Nakao

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76867 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film. During the period until the barrier layer having also the function of enhancing tight adhesion, it becomes possible to retain sufficient tight adhesion of a wiring member and prevent peel-off of the wiring member.

摘要翻译： 在半导体基板上形成具有凹部的层间绝缘膜。 在凹部的内表面和绝缘膜的上表面上形成紧密粘合膜。 粘附层的表面覆盖有由含有第一金属元素的Cu合金制成的辅助膜。 包含除了第一金属元件之外的第二金属元件的导电构件被嵌入在凹部中，并且沉积在辅助膜上。 进行热处理，使辅助膜中的第一金属元素的原子在凹部的内表面分离。 如果辅助膜直接沉积在层间绝缘膜的表面上，则粘合层包含用于增强辅助膜的紧密粘附的元件。 在阻隔层也具有增强紧密附着力的时段期间，可以保持布线部件的足够的紧密粘合性并防止布线部件的剥离。

公开(公告)号：US07795141B2

公开(公告)日：2010-09-14

申请号：US12216832

申请日：2008-07-11

申请人： Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Hideki Kitada ,  Yoshiyuki Nakano

发明人： Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Hideki Kitada ,  Yoshiyuki Nakano

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.

摘要翻译： （a1）在半导体基板上形成的层间绝缘膜中形成有凹部。 （a2）通过CVD形成Mn的第一膜，所述第一膜覆盖所述凹部的内表面和所述绝缘膜的上表面。 （a3）基本上由Cu组成的导电材料沉积在第一膜上，以将导电材料嵌入凹部中。 （a4）半导体衬底退火。 在形成阻挡层的同时具有提高紧密粘合性的功能的期间，能够确保布线部件的充分的密合性，防止配线部件的剥离。

公开(公告)号：US20080286960A1

公开(公告)日：2008-11-20

申请号：US12216832

申请日：2008-07-11

申请人： Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Hideki Kitada ,  Yoshiyuki Nakao

发明人： Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Hideki Kitada ,  Yoshiyuki Nakao

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.

摘要翻译： （a1）在半导体基板上形成的层间绝缘膜中形成有凹部。 （a2）通过CVD形成Mn的第一膜，所述第一膜覆盖所述凹部的内表面和所述绝缘膜的上表面。 （a3）基本上由Cu组成的导电材料沉积在第一膜上，以将导电材料嵌入凹部中。 （a4）半导体衬底退火。 在形成阻挡层的同时具有提高紧密粘合性的功能的期间，能够确保布线部件的充分的密合性，防止配线部件的剥离。