公开(公告)号：US20120014183A1

公开(公告)日：2012-01-19

申请号：US12837835

申请日：2010-07-16

申请人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Andrew J. Franklin

IPC分类号： G11C16/04

CPC分类号： G11C16/0466

摘要： A non-volatile memory (NVM) cell structure comprises an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

摘要翻译： 非易失性存储器（NVM）单元结构包括NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS数据晶体管和连接到数据存储节点的栅电极。

公开(公告)号：US07656698B1

公开(公告)日：2010-02-02

申请号：US11656650

申请日：2007-01-23

申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang (James) Lin ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang (James) Lin ,  Andrew J. Franklin

IPC分类号： G11C11/00

CPC分类号： G11C14/0063 ,  G11C16/0441

摘要： A 4-transistor non-volatile memory (NVM) cell includes a static random access memory (SRAM) cell structure. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the SRAM cell structure, allows an entire array to be programmed at one cycle. Equalize transistors are utilized to obtain more uniform voltage on the floating gates after an erase operation. Utilization of decoupling pas gates during a read operation results in more charge difference on floating gates of programmed and erased cells.

摘要翻译： 4晶体管非易失性存储器（NVM）单元包括静态随机存取存储器（SRAM）单元结构。 NVM单元采用反向Fowler-Nordheim隧道编程技术，其结合SRAM单元结构允许在一个周期对整个阵列进行编程。 利用均衡晶体管在擦除操作之后在浮动栅极上获得更均匀的电压。 在读取操作期间使用去耦pas门导致编程和擦除单元的浮动栅极上的更多的电荷差异。

公开(公告)号：US07126866B1

公开(公告)日：2006-10-24

申请号：US10215699

申请日：2002-08-10

申请人： Pavel Poplevine ,  Ernes Ho ,  Hengyang Lin ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Ernes Ho ,  Hengyang Lin ,  Andrew J. Franklin

IPC分类号： G11C7/00

CPC分类号： G11C17/12 ,  G11C7/12

摘要： In a ROM structure, power consumption is reduced by providing for pre-discharging of only the bit line corresponding to the memory location that is being read. Column select lines are coupled to logic to switch in a pre-discharging circuit prior to reading, and to disconnect, from the pre-discharging circuit during reading, only the bit line corresponding to the memory location being read.

摘要翻译： 在ROM结构中，通过仅对与正在读取的存储器位置相对应的位线进行预放电来降低功耗。 列选择线耦合到逻辑以在读取之前切换预放电电路，并且在读取期间从预放电电路断开，仅读取对应于存储器位置的位线。

公开(公告)号：US06618282B1

公开(公告)日：2003-09-09

申请号：US10213845

申请日：2002-08-07

申请人： Pavel Poplevine ,  Hengyang Lin ,  Andrew J. Franklin ,  Umer Ahmed Khan

发明人： Pavel Poplevine ,  Hengyang Lin ,  Andrew J. Franklin ,  Umer Ahmed Khan

IPC分类号： G11C1700

CPC分类号： G11C7/106 ,  G11C7/1012 ,  G11C7/1051 ,  G11C17/12

摘要： A ROM system which provides for reduced size and power consumption. This ROM systems allows for inverting the programming and sensing of information in bit cells of the ROM to reduce the number of transistors in bit cells of the ROM. Further bit cells of the ROM provide that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed.

摘要翻译： 一种提供减小尺寸和功耗的ROM系统。 该ROM系统允许反转ROM的位单元中的信息的编程和感测以减少ROM的位单元中的晶体管的数量。 ROM的其它位单元提供了当晶体管设置在位线和字线之间时，第一类型的信息被存储在位单元中，并且当第二类型的信息在 位线和字线。 在晶体管形成在位线和字线之间的情况下，在位单元中提供位线和可以在衬底中形成晶体管漏极的区域之间的接触。 在位单元在字线和位线之间不提供晶体管的情况下，在位线和可以形成晶体管漏极的区域之间不提供接触。

公开(公告)号：US07069461B1

公开(公告)日：2006-06-27

申请号：US10351056

申请日：2003-01-24

申请人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

发明人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

IPC分类号： G06F1/04

CPC分类号： G11C5/14 ,  G11C7/1072 ,  G11C11/4074

摘要： The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.

摘要翻译： 响应于时钟信号的频率的变化来调整存储器系统的电源电压。 存储器系统测量从数据在存储器的输出到下一个时钟边沿的数据有效的时间，以确定时序值。 当时钟频率从第一频率变化到第二频率时，定时值从第一值变为第二值。 改变电源电压的大小，将定时值返回到第一个值。

公开(公告)号：US06420217B1

公开(公告)日：2002-07-16

申请号：US09632375

申请日：2000-08-03

申请人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

发明人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

IPC分类号： H01L2182

CPC分类号： H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse. The transistor includes: a well region in a substrate, the well region forming the drain of the transistor; an insulating trench in the well; and a polysilicon gate extending over a portion of the substrate, a portion of the well and a portion of the trench, wherein upon reverse-biasing the junction between the well and the substrate a depletion region is formed which encompasses at least the entire portion of the surface region of the well over which the polysilicon extends.

摘要翻译： 集成的熔丝元件能够被编程为低电压工艺技术中的高电阻。 熔丝包括未掺杂的多晶硅层和硅化物层的堆叠。 施加在堆叠上的电压增加直到发生第一附聚事件，由此在硅化物层中形成不连续性。 电流进一步增加以引起第二聚集事件，从而增加不连续性的大小。 每个附聚事件会增加保险丝的电阻。 能够保持高电压的延伸漏极MOS晶体管与保险丝串联连接，以对熔丝进行编程。 晶体管包括：衬底中的阱区，形成晶体管的漏极的阱区; 井中的绝缘沟槽; 以及在所述衬底的一部分上延伸的多晶硅栅极，所述阱的一部分和所述沟槽的一部分，其中在反向偏置所述阱和所述衬底之间的结点时，形成耗尽区，所述耗尽区至少包括 多晶硅延伸的阱的表面区域。

公开(公告)号：US06218688B1

公开(公告)日：2001-04-17

申请号：US09280888

申请日：1999-03-29

申请人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

发明人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

IPC分类号： H01L27095

CPC分类号： H01L27/0811

摘要： The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.

摘要翻译： 在本发明中，通过形成肖特基二极管通过场氧化物隔离区域，由常规肖特基二极管消耗的硅壳体减少。 通过场氧化物隔离区域的蚀刻需要额外的蚀刻时间，其通过常规蚀刻步骤提供，其通常在接触形成期间指定50-100％的过蚀刻。

公开(公告)号：US6122204A

公开(公告)日：2000-09-19

申请号：US320413

申请日：1999-05-26

申请人： Pavel Poplevine ,  Alexander Kalnitsky ,  Albert Bergemont

发明人： Pavel Poplevine ,  Alexander Kalnitsky ,  Albert Bergemont

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C7/065

摘要： A sense amplifier places a low positive voltage, such as 0.1 to 0.3 volts, on a bit line instead of ground when a memory cell is read by utilizing a current source circuit to output a reference current that biases a Schottky diode. The current source circuit is implemented with a Schottky diode that utilizes the reverse-biased leakage current of the diode to form the reference current. The current source circuit can also be implemented with a current mirror circuit.

摘要翻译： 当通过利用电流源电路读出存储单元以输出偏置肖特基二极管的参考电流时，读出放大器将位置线上的低正电压（例如0.1至0.3伏特）置于地线上而不是接地。 电流源电路用肖特基二极管实现，其利用二极管的反向偏置漏电流形成参考电流。 电流源电路也可以用电流镜电路来实现。

公开(公告)号：US6049202A

公开(公告)日：2000-04-11

申请号：US191140

申请日：1998-11-13

申请人： Pavel Poplevine ,  Alexander Kalnitsky ,  Albert Bergemont

发明人： Pavel Poplevine ,  Alexander Kalnitsky ,  Albert Bergemont

IPC分类号： G05F3/24 ,  G05F3/16 ,  G05F3/02

CPC分类号： G05F3/245

摘要： A reference current generator outputs a reference current which is insensitive to temperature variations by utilizing two gated diodes to output currents. The currents output by the gated diodes are divided to produce the reference current which, due to the cancellation of terms, is defined by the ratio of the gate areas of the gated diodes. In addition, by utilizing two oscillators, which run at different frequencies, to drive the gated diodes, the reference current may alternately be defined by the ratio of the two frequencies.

摘要翻译： 参考电流发生器通过利用两个门控二极管输出电流来输出对温度变化不敏感的参考电流。 由门控二极管输出的电流被分压以产生参考电流，由于术语的消除，其由门控二极管的栅极面积的比定义。 此外，通过利用以不同频率运行的两个振荡器来驱动门控二极管，参考电流可以交替地由两个频率的比率来定义。

公开(公告)号：US08284600B1

公开(公告)日：2012-10-09

申请号：US12702061

申请日：2010-02-08

申请人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Hengyang James Lin

发明人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Hengyang James Lin

IPC分类号： G11C11/34

CPC分类号： G11C16/0441

摘要： A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.

摘要翻译： 非易失性存储器（NVM）单元包括具有共同连接的源极，漏极和体区电极的NMOS控制晶体管和连接到存储节点的栅电极; 具有共连接的源极，漏极和体区电极的PMOS擦除晶体管和连接到存储节点的栅电极; 具有源极，漏极和体区电极的NMOS数据晶体管和连接到存储节点的栅极，所述体区电极连接到公共体节点; 所述第一NMOS栅极晶体管具有连接到所述NMOS数据晶体管的漏电极的源电极，漏电极，连接到所述公共体节点的体区电极和栅电极; 以及第二NMOS栅极晶体管，其具有连接到NMOS数据晶体管的源电极的漏电极，源电极，连接到公共体节点的体区电极和栅电极。