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    3 TRANSISTOR (N/P/N) NON-VOLATILE MEMORY CELL WITHOUT PROGRAM DISTURB
    3.
    发明申请
    3 TRANSISTOR (N/P/N) NON-VOLATILE MEMORY CELL WITHOUT PROGRAM DISTURB 审中-公开
    3晶体管（N / P / N）不具有程序干扰的非易失性存储单元

    公开(公告)号：US20120014183A1

    公开(公告)日：2012-01-19

    申请号：US12837835

    申请日：2010-07-16

    申请人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Andrew J. Franklin

    发明人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Andrew J. Franklin

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0466

    摘要： A non-volatile memory (NVM) cell structure comprises an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

    摘要翻译： 非易失性存储器（NVM）单元结构包括NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS数据晶体管和连接到数据存储节点的栅电极。

    5-transistor non-volatile memory cell
    4.
    发明授权
    5-transistor non-volatile memory cell 有权
    5晶体管非易失性存储单元

    公开(公告)号：US08284600B1

    公开(公告)日：2012-10-09

    申请号：US12702061

    申请日：2010-02-08

    申请人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Hengyang James Lin

    发明人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Hengyang James Lin

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0441

    摘要： A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.

    摘要翻译： 非易失性存储器（NVM）单元包括具有共同连接的源极，漏极和体区电极的NMOS控制晶体管和连接到存储节点的栅电极; 具有共连接的源极，漏极和体区电极的PMOS擦除晶体管和连接到存储节点的栅电极; 具有源极，漏极和体区电极的NMOS数据晶体管和连接到存储节点的栅极，所述体区电极连接到公共体节点; 所述第一NMOS栅极晶体管具有连接到所述NMOS数据晶体管的漏电极的源电极，漏电极，连接到所述公共体节点的体区电极和栅电极; 以及第二NMOS栅极晶体管，其具有连接到NMOS数据晶体管的源电极的漏电极，源电极，连接到公共体节点的体区电极和栅电极。

    All-NMOS 4-transistor non-volatile memory cell
    5.
    发明授权
    All-NMOS 4-transistor non-volatile memory cell 有权
    全NMOS 4晶体管非易失性存储单元

    公开(公告)号：US08363469B1

    公开(公告)日：2013-01-29

    申请号：US12698318

    申请日：2010-02-02

    申请人： Pavel Poplevine ,  Umer Khan ,  Hengyang (James) Lin ,  Andrew J. Franklin

    发明人： Pavel Poplevine ,  Umer Khan ,  Hengyang (James) Lin ,  Andrew J. Franklin

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： H01L27/115

    摘要： A non-volatile memory cell includes NMOS programming, read, erase, and control transistors having gate electrodes connected to a storage node. The erase and control transistors have interconnected source, drain, and bulk electrodes. The cell is programmed by setting source, drain, bulk, and gate electrodes of all transistors to a positive voltage. An inhibiting voltage is applied to source, drain, and bulk electrodes of the read transistor, while setting source and drain electrodes of the programming transistor to the positive voltage and the bulk electrode of the programming transistor to the positive voltage or the inhibiting voltage. Source, drain, and bulk electrodes of the control transistor are then ramped to a negative control voltage while ramping source, drain, and bulk electrodes of the erase transistor to a negative erase voltage and then back to the positive voltage. Source, drain. bulk, and gate electrodes of the programming, erase, and control transistors are then returned to the positive voltage, while setting the source, drain, and bulk electrodes of the read transistor to the inhibiting voltage.

    摘要翻译： 非易失性存储单元包括具有连接到存储节点的栅极的NMOS编程，读取，擦除和控制晶体管。 擦除和控制晶体管具有互连的源极，漏极和体电极。 通过将所有晶体管的源极，漏极，体积和栅极电极设置为正电压来对单元进行编程。 在将编程晶体管的源极和漏极电极设置为正电压和编程晶体管的体电极至正电压或抑制电压的同时，将读取晶体管的源极，漏极和体电极施加抑制电压。 然后，控制晶体管的源极，漏极和体电极斜坡到负的控制电压，同时将擦除晶体管的源极，漏极和体电极斜缓到负的擦除电压，然后返回到正的电压。 来源，流失。 然后将编程，擦除和控制晶体管的体积和栅电极返回到正电压，同时将读取晶体管的源极，漏极和体电极设置为抑制电压。

    High density ROM architecture
    6.
    发明授权
    High density ROM architecture 有权
    高密度ROM架构

    公开(公告)号：US06642587B1

    公开(公告)日：2003-11-04

    申请号：US10214021

    申请日：2002-08-07

    申请人： Pavel Poplevine ,  Hengyang Lin ,  Andrew J. Franklin ,  Ernes Ho

    发明人： Pavel Poplevine ,  Hengyang Lin ,  Andrew J. Franklin ,  Ernes Ho

    IPC分类号： H01L2976

    CPC分类号： H01L27/11246 ,  G11C17/123 ,  H01L27/112

    摘要： A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed. Further, where a bit cell does not provide a transistor between the bit line and the word line a bit cell region in the substrate can consist substantially of an isolating dielectric material.

    摘要翻译： 提供减小尺寸和功耗的ROM阵列。 ROM的位单元提供了当晶体管设置在位线和字线之间时，第一类型的信息被存储在位单元中，并且第二类型的信息被存储在单元中，当没有晶体管设置在单元之间时 位线和字线。 在晶体管形成在位线和字线之间的情况下，在位单元中提供位线和可以在衬底中形成晶体管漏极的区域之间的接触。 在位单元在字线和位线之间不提供晶体管的情况下，在位线和可以形成晶体管漏极的区域之间不提供接触。 此外，在位单元不在位线和字线之间提供晶体管的情况下，衬底中的位单元区域可以基本上由隔离电介质材料组成。

    4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRUCTURE
    7.
    发明申请
    4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRUCTURE 有权
    具有PMOS-NMOS-PMOS-NMOS结构的4晶体管非易失性存储单元

    公开(公告)号：US20110242898A1

    公开(公告)日：2011-10-06

    申请号：US12751012

    申请日：2010-03-31

    申请人： Pavel Poplevine ,  Ernes Ho ,  Hengyang James Lin ,  Andrew J. Franklin

    发明人： Pavel Poplevine ,  Ernes Ho ,  Hengyang James Lin ,  Andrew J. Franklin

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/0441 ,  G11C16/10

    摘要： A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

    摘要翻译： 非易失性存储器（NVM）单元结构包括具有源极，漏极和体区电极的PMOS程序晶体管和连接到数据存储节点的栅电极; NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅电极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS读取晶体管和连接到数据存储节点的栅电极。

    4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure
    8.
    发明授权
    4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure 有权
    具有PMOS-NMOS-PMOS-NMOS结构的4晶体管非易失性存储单元

    公开(公告)号：US08213227B2

    公开(公告)日：2012-07-03

    申请号：US12751012

    申请日：2010-03-31

    申请人： Pavel Poplevine ,  Ernes Ho ,  Hengyang (James) Lin ,  Andrew J. Franklin

    发明人： Pavel Poplevine ,  Ernes Ho ,  Hengyang (James) Lin ,  Andrew J. Franklin

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/0441 ,  G11C16/10

    摘要： A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

    摘要翻译： 非易失性存储器（NVM）单元结构包括具有源极，漏极和体区电极的PMOS程序晶体管和连接到数据存储节点的栅电极; NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅电极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS读取晶体管和连接到数据存储节点的栅电极。

    Low power ROM architecture
    9.
    发明授权
    Low power ROM architecture 有权
    低功耗ROM架构

    公开(公告)号：US07126866B1

    公开(公告)日：2006-10-24

    申请号：US10215699

    申请日：2002-08-10

    申请人： Pavel Poplevine ,  Ernes Ho ,  Hengyang Lin ,  Andrew J. Franklin

    发明人： Pavel Poplevine ,  Ernes Ho ,  Hengyang Lin ,  Andrew J. Franklin

    IPC分类号： G11C7/00

    CPC分类号： G11C17/12 ,  G11C7/12

    摘要： In a ROM structure, power consumption is reduced by providing for pre-discharging of only the bit line corresponding to the memory location that is being read. Column select lines are coupled to logic to switch in a pre-discharging circuit prior to reading, and to disconnect, from the pre-discharging circuit during reading, only the bit line corresponding to the memory location being read.

    摘要翻译： 在ROM结构中，通过仅对与正在读取的存储器位置相对应的位线进行预放电来降低功耗。 列选择线耦合到逻辑以在读取之前切换预放电电路，并且在读取期间从预放电电路断开，仅读取对应于存储器位置的位线。

    Non-volatile memory cell with improved programming technique and density
    10.
    发明授权
    Non-volatile memory cell with improved programming technique and density 有权
    具有改进的编程技术和密度的非易失性存储单元

    公开(公告)号：US07453726B1

    公开(公告)日：2008-11-18

    申请号：US11656609

    申请日：2007-01-23

    申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Andrew Cao ,  Ernes Ho

    发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Andrew Cao ,  Ernes Ho

    IPC分类号： G11C11/34 ,  G11C14/00

    CPC分类号： G11C14/00

    摘要： A single 4-transistor non-volatile memory (NVM) cell includes a shared static random access memory cell. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the shared SRAM cell structure, allows an entire cell array to be programmed at two cycles. A single NVM cell approach with shared SRAM allows a 50% area reduction with an insignificant increase in program time.

    摘要翻译： 单个4晶体管非易失性存储器（NVM）单元包括共享静态随机存取存储单元。 NVM单元利用反向Fowler-Nordheim隧道编程技术，其结合共享的SRAM单元结构，允许在两个周期对整个单元阵列进行编程。 具有共享SRAM的单个NVM单元方案允许减少50％的面积，并且程序时间不会显着增加。