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公开(公告)号：US10693674B2
公开(公告)日：2020-06-23
申请号：US15882494
申请日：2018-01-29
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee Mishra , Richard Dominic Wietfeldt , Radu Pitigoi-Aron
Abstract: Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.
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公开(公告)号：US10572438B1
公开(公告)日：2020-02-25
申请号：US16295046
申请日：2019-03-07
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee Mishra , Richard Dominic Wietfeldt , Christopher Kong Yee Chun , Radu Pitigoi-Aron
Abstract: Systems, methods, and apparatus for improving end-to-end timing closure of a serial bus are described. An apparatus is coupled to a serial bus through an interface circuit and has a clock generator that provides a first clock signal, a delay circuit that is adapted to generate a second clock signal by delaying the first clock signal, and a controller that is configured to cause the interface circuit to use an edge of the first clock signal to initiate transmission of a first data bit over the serial bus during a write operation, delay the first clock signal to obtain a second clock signal, and cause the interface circuit to use an edge of the second clock signal to capture a second data bit from the serial bus during a read operation. The edge of the second clock signal is delayed with respect to the edge of the first clock signal.
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公开(公告)号：US10402365B2
公开(公告)日：2019-09-03
申请号：US16201369
申请日：2018-11-27
Applicant: QUALCOMM Incorporated
Inventor： Radu Pitigoi-Aron , Lalan Jee Mishra , Richard Dominic Wietfeldt
IPC: G06F13/42 , G06F13/364 , H04L5/00
Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in multiple modes that employ additional wires for communicating data such that the bus width may be dynamically extended to improve bandwidth and/or throughput. One method includes transmitting a set of frames or sequences of symbols configured to carry up to a maximum number of data bytes over the serial bus, transmitting control signaling over a first data lane and the clock lane after the set of frames or sequences of symbols has been transmitted, and transmitting a first signal over a second data lane while transmitting the control signaling that may indicate whether the set of frames or sequences of symbols includes padding. The first signal may indicate a number of valid bytes or words in the set of frames or sequences of symbols.
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公开(公告)号：US20190146944A1
公开(公告)日：2019-05-16
申请号：US16242920
申请日：2019-01-08
Applicant: QUALCOMM Incorporated
Inventor： Radu Pitigoi-Aron , Richard Dominic Wietfeldt
IPC: G06F13/42 , G06F13/40 , G06F13/364
Abstract: A device is provided that has a bus including a first line and a second line. A first set of devices are coupled to the bus and, in a first mode of operation, configured to use the first line for data transmissions and use the second line for a first clock signal. One or more additional lines are connected between two or more of the devices in the first set of devices for transmitting signaling between the two or more devices. A second set of devices are configured to use the bus and at least one of the additional lines for data transmissions in a second mode of operation, where in the second mode of operation symbols are encoded across the first line, the second line, and the at least one of the additional lines.
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公开(公告)号：US10140242B2
公开(公告)日：2018-11-27
申请号：US15242368
申请日：2016-08-19
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee Mishra , Richard Dominic Wietfeldt , Radu Pitigoi-Aron
Abstract: In an aspect, an integrated circuit obtains a set of general purpose input/output (GPIO) signals for one or more peripheral devices, obtains a first virtual GPIO packet that includes the set of GPIO signals independent of a central processing unit, and transmits the first virtual GPIO packet to the one or more peripheral devices over an I3C bus independent of the central processing unit. The integrated circuit may further obtain a set of configuration signals for configuring one or more GPIO pins of the one or more peripheral devices, obtain a second virtual GPIO packet that includes the set of configuration signals independent of the central processing unit, and transmit the second virtual GPIO packet to the one or more peripheral devices over the I3C bus independent of the central processing unit.
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Patent Agency Ranking
公开(公告)号：US09880965B2
公开(公告)日：2018-01-30
申请号：US14850809
申请日：2015-09-10
Applicant: QUALCOMM Incorporated
CPC classification number: G06F13/4221 , G06F1/10 , G06F13/385
Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.
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27.发明申请公开(公告)号：US20170075852A1
公开(公告)日：2017-03-16
申请号：US15242368
申请日：2016-08-19
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee Mishra , Richard Dominic Wietfeldt , Radu Pitigoi-Aron
IPC: G06F13/42 , G06F15/17 , G06F13/40 , G06F15/177
CPC classification number: G06F13/4282 , G06F13/385 , G06F13/4022 , G06F15/17 , G06F15/177
Abstract: In an aspect, an integrated circuit obtains a set of general purpose input/output (GPIO) signals for one or more peripheral devices, obtains a first virtual GPIO packet that includes the set of GPIO signals independent of a central processing unit, and transmits the first virtual GPIO packet to the one or more peripheral devices over an I3C bus independent of the central processing unit. The integrated circuit may further obtain a set of configuration signals for configuring one or more GPIO pins of the one or more peripheral devices, obtain a second virtual GPIO packet that includes the set of configuration signals independent of the central processing unit, and transmit the second virtual GPIO packet to the one or more peripheral devices over the I3C bus independent of the central processing unit.
Abstract translation: 一方面，集成电路获得用于一个或多个外围设备的一组通用输入/输出（GPIO）信号，获得独立于中央处理单元的包括一组GPIO信号的第一虚拟GPIO分组，并发送 第一个虚拟GPIO数据包通过独立于中央处理单元的I3C总线上的一个或多个外设。 集成电路还可以获得用于配置一个或多个外围设备的一个或多个GPIO引脚的一组配置信号，获得包括独立于中央处理单元的一组配置信号的第二虚拟GPIO分组，并且发送第二个 虚拟GPIO数据包到I3C总线上的一个或多个外设，独立于中央处理器。
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28.发明申请APPARATUS AND METHODS FOR TIMESTAMPING IN A SYSTEM SYNCHRONIZING CONTROLLER AND SENSORS 审中-公开用于系统同步控制器和传感器的设备和方法公开(公告)号：US20170041688A1
公开(公告)日：2017-02-09
申请号：US15299408
申请日：2016-10-20
Applicant: QUALCOMM Incorporated
Inventor： Radu Pitigoi-Aron , Leonid Sheynblat , Carlos Puig , Justin Black , Rashmi Kulkarni
CPC classification number: H04Q9/00 , G06F1/14 , G06F1/3234 , H04J3/0661 , H04J3/0685 , H04Q9/04 , H04Q2209/30 , H04Q2209/753 , H04Q2209/826 , H04Q2209/883 , H04W84/18
Abstract: Disclosed are methods and apparatus for synchronizing a controller and sensors in a system. A timestamp is provided in a host controller of an interface event on an interface coupled with host controller through detecting a message from a sensor on the interface that identifies the issuance of the interface event caused by the sensor at a first time. In response, the controller issues first and second events on the interface at respective second and third times, while concurrently counting cycles of a clock in the controller after each issuance. The controller also receives a first and second sensor counts representing the internal sensor clock times noted for the first and second events. The controller may then accurately calculate the timestamp of the interface event corresponding to the first time based on both internal controller counts and the sensor counts without needing a timestamp from the sensor directly.
Abstract translation: 公开了用于使系统中的控制器和传感器同步的方法和装置。 在与主机控制器耦合的接口的接口事件的主机控制器中，通过从接口上的传感器检测到消息，在第一时间识别由传感器引起的接口事件的发出，提供时间戳。 作为响应，控制器在相应的第二和第三次在接口上发出第一和第二事件，同时在每次发布之后同时对控制器中的时钟的周期进行计数。 控制器还接收表示第一和第二事件所指示的内部传感器时钟时间的第一和第二传感器计数。 然后，控制器可以基于内部控制器计数和传感器计数来准确地计算与第一次相对应的接口事件的时间戳，而不需要直接来自传感器的时间戳。
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公开(公告)号：US20160124896A1
公开(公告)日：2016-05-05
申请号：US14925612
申请日：2015-10-28
Applicant: QUALCOMM Incorporated
Inventor： Radu Pitigoi-Aron , Justin Black
IPC: G06F13/42 , G06F13/364
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/4282 , H04L25/4923
Abstract: A device is provided comprising a shared bus including a first and a second line, a first subset of devices and a second subset of devices coupled to the shared bus. The first subset of devices may be configured to operate according to a first protocol mode. The second subset of devices may be configured to operate according to a second protocol mode, wherein the second protocol mode is distinct from the first protocol mode. A first device within the first subset of devices may include a receiver circuit adapted to adjust a signal transition occurring on the first line while the second line is in a first logical state so that the signal transition instead occurs when the second line is in a second logical state. The signal transition is adjusted only if it occurs within a threshold amount of time from a second transition on the second line.
Abstract translation: 提供了一种包括共享总线的设备，该共享总线包括第一和第二线路，设备的第一子集以及耦合到共享总线的设备的第二子集。 设备的第一子集可以被配置为根据第一协议模式进行操作。 设备的第二子集可以被配置为根据第二协议模式进行操作，其中第二协议模式与第一协议模式不同。 设备的第一子集内的第一设备可以包括接收机电路，其适于在第二行处于第一逻辑状态时调整发生在第一行上的信号转换，从而当第二行处于第二行时发生信号转换 逻辑状态。 只有当信号转换发生在从第二条线路上的第二转变开始的阈值时间内时才调整信号转换。
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30.发明申请公开(公告)号：US20160077995A1
公开(公告)日：2016-03-17
申请号：US14850809
申请日：2015-09-10
Applicant: QUALCOMM Incorporated
CPC classification number: G06F13/4221 , G06F1/10 , G06F13/385
Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.
Abstract translation: 提供了一个从处理器接收GPIO信号发送组件的虚拟GPIO接口。 虚拟GPIO接口以传统方式通过GPIO引脚传输GPIO信号发送组的一部分。 然而，虚拟GPIO接口将GPIO信号发送组的剩余部分提供给有限状态机，将剩余部分中的GPIO信号序列化为虚拟GPIO信号帧。 一个经过修改的UART接口可以响应UART过采样时钟的周期，通过UART发送引脚发送帧。
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