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    Write word-line assist circuitry for a byte-writeable memory
    23.
    发明授权
    Write word-line assist circuitry for a byte-writeable memory 有权
    为字节可写存储器写入字线辅助电路

    公开(公告)号：US09202555B2

    公开(公告)日：2015-12-01

    申请号：US13656593

    申请日：2012-10-19

    Applicant: QUALCOMM Incorporated

    Inventor： Changho Jung ,  Nishith Desai ,  Sei Seung Yoon

    IPC: G11C11/00 ,  G11C11/418 ,  G11C8/08 ,  G11C11/419

    CPC classification number: G11C11/418 ,  G11C8/08 ,  G11C11/419

    Abstract: A write-assisted memory. The write-assisted memory includes a word-line decoder that is implemented within a low VDD power domain. The write-assisted memory also includes a write-segment controller that is partially implemented within the low VDD power domain and is partially implemented within a high VDD power domain. The write-assisted memory further includes a local write word-line decoder that is implemented within the high VDD power domain.

    Abstract translation: 写辅助记忆。 写辅助存储器包括在低VDD功率域内实现的字线解码器。 写辅助存储器还包括写入段控制器，其部分地在低VDD功率域内实现，并且部分地在高VDD功率域内实现。 写辅助存储器还包括在高VDD功率域内实现的本地写字线解码器。

    Write driver for write assistance in memory device
    24.
    发明授权
    Write driver for write assistance in memory device 有权
    在内存设备中写入写入驱动程序

    公开(公告)号：US09030893B2

    公开(公告)日：2015-05-12

    申请号：US13760988

    申请日：2013-02-06

    Applicant: QUALCOMM Incorporated

    Inventor： Changho Jung ,  Nishith Desai ,  Rakesh Vattikonda

    IPC: G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/419 ,  G11C11/408 ,  G11C5/14

    CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/00 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/419

    Abstract: A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMlower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP≧VddM>VddMlower.

    Abstract translation: 提供一种写辅助驱动器电路，即使当电源电压降低时，也可以在写入操作中帮助存储器单元（例如，易失性存储器位单元）来保持存储器核心处的电压足够高以用于正确的写入操作。 写辅助驱动器电路可以被配置为在待机操作模式期间向位单元核提供存储器电源电压VddM。 在写入操作模式中，写入辅助驱动器电路可以向位单元核心以及本地写入位线（lwbl）和本地写入位线条（lwblb）中的至少一个提供降低的存储器电源电压VddMlower。 此外，写辅助驱动器电路还可以向本地写入字线（lww1）提供外围电源电压VddP，其中VddP≥VddM> VddMlower。

    HIGH-SPEED MEMORY WRITE DRIVER CIRCUIT WITH VOLTAGE LEVEL SHIFTING FEATURES
    25.
    发明申请
    HIGH-SPEED MEMORY WRITE DRIVER CIRCUIT WITH VOLTAGE LEVEL SHIFTING FEATURES 有权
    具有电压水平移位功能的高速存储器写入驱动器电路

    公开(公告)号：US20140254293A1

    公开(公告)日：2014-09-11

    申请号：US13784830

    申请日：2013-03-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： Nishith Desai ,  Rakesh Vattikonda ,  Changho Jung

    IPC: G11C7/12

    CPC classification number: G11C7/1096 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/417 ,  G11C2207/2227

    Abstract: Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power. The write driver circuit shifts or adjusts voltage levels between a first voltage domain to a second voltage domain. In one example, the write driver circuit is coupled to a global write bitline and a local write bitline that is coupled to one or more bitcells (of SRAM memory). The write driver circuit converts a first voltage level at the global write bitline to a second voltage level at the local write bitline during a write operation.

    Abstract translation: 本文提供了能够在双电压域存储器架构中有效操作的快速，高能量写入驱动器的各个方面。 具体来说，这里描述的写入驱动器的各个方面将高速驱动器与电压电平转换能力相结合，可以在减少使用较低功耗的硅片区域的同时有效地实现。 写驱动器电路移位或调整第一电压域与第二电压域之间的电压电平。 在一个示例中，写驱动器电路耦合到耦合到SRAM存储器的一个或多个位单元的全局写位线和本地写位线。 写入驱动器电路在写操作期间将全局写位线处的第一电压电平转换为本地写位线处的第二电压电平。

    WRITE WORD-LINE ASSIST CIRCUITRY FOR A BYTE-WRITEABLE MEMORY
    26.
    发明申请
    WRITE WORD-LINE ASSIST CIRCUITRY FOR A BYTE-WRITEABLE MEMORY 有权
    用于字节可写存储器的写字线辅助电路

    公开(公告)号：US20140112061A1

    公开(公告)日：2014-04-24

    申请号：US13656593

    申请日：2012-10-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： Changho Jung ,  Nishith Desai ,  Sei Seung Yoon

    IPC: G11C7/00

    CPC classification number: G11C11/418 ,  G11C8/08 ,  G11C11/419

    Abstract: A write-assisted memory. The write-assisted memory includes a word-line decoder that is implemented within a low VDD power domain. The write-assisted memory also includes a write-segment controller that is partially implemented within the low VDD power domain and is partially implemented within a high VDD power domain. The write-assisted memory further includes a local write word-line decoder that is implemented within the high VDD power domain.

    Abstract translation: 写辅助记忆。 写辅助存储器包括在低VDD功率域内实现的字线解码器。 写辅助存储器还包括写入段控制器，其部分地在低VDD功率域内实现，并且部分地在高VDD功率域内实现。 写辅助存储器还包括在高VDD功率域内实现的本地写字线解码器。

    Techniques for reducing rock bottom leakage in memory
    28.
    发明授权
    Techniques for reducing rock bottom leakage in memory 有权

    公开(公告)号：US11170845B1

    公开(公告)日：2021-11-09

    申请号：US16928658

    申请日：2020-07-14

    Applicant: QUALCOMM Incorporated

    Inventor： Arun Babu Pallerla ,  Derek Yang ,  Chulmin Jung ,  Changho Jung

    IPC: G11C8/08 ,  G11C11/418

    Abstract: Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.

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