公开(公告)号：US11462263B2

公开(公告)日：2022-10-04

申请号：US17131172

申请日：2020-12-22

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Arun Babu Pallerla ,  Chulmin Jung

IPC: G11C11/419 ,  G06F3/06 ,  G11C11/418 ,  H03K19/20 ,  H04M1/02

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A column multiplexer selects from a plurality of columns using a pair of pass transistor for each column. The column multiplexer drives a true input node and a complement input node of an output data latch.

公开(公告)号：US11361817B2

公开(公告)日：2022-06-14

申请号：US17002082

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Changho Jung ,  Sung Son ,  Jason Cheng ,  Yandong Gao ,  Chulmin Jung ,  Venugopal Boynapalli

IPC: G11C16/04 ,  G11C11/4096 ,  G11C11/408 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/4094

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

公开(公告)号：US11302388B2

公开(公告)日：2022-04-12

申请号：US17002010

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Changho Jung

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03K19/20

Abstract: A word line decoder for pseudo-triple-port memory is provided that includes a first logic gate for decoding a word line address to a first word line in a word line pair and a first word line clock signal. The decoder further includes a second logic gate for decoding a word line address to a second word line in the word line pair and a second word line clock signal.

公开(公告)号：US11092646B1

公开(公告)日：2021-08-17

申请号：US16794105

申请日：2020-02-18

Applicant: QUALCOMM Incorporated

Inventor： Sonia Ghosh ,  Changho Jung ,  Chulmin Jung

IPC: G01R31/3181 ,  G01R31/317 ,  G01J1/18

Abstract: According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.

公开(公告)号：US09997208B1

公开(公告)日：2018-06-12

申请号：US15473124

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Po-Hung Chen ,  Fahad Ahmed ,  Changho Jung ,  Sei Seung Yoon ,  David Li

IPC: G11C8/08 ,  G11C5/14 ,  H03K19/0185 ,  G11C8/10 ,  G11C7/12

CPC classification number: G11C5/147 ,  G11C7/12 ,  G11C8/10 ,  H03K3/356069 ,  H03K19/018528

Abstract: A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.

公开(公告)号：US09978444B2

公开(公告)日：2018-05-22

申请号：US15077636

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu Kwok ,  Changho Jung

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/08 ,  G11C7/22 ,  G11C8/18 ,  G11C7/10

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/227 ,  G11C8/18 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A memory and a method for operating the memory are presented. The memory includes a memory cell, a sense amplifier configured to sense read data from the memory cell, a write driver configured to provide write data to the memory cell, a first circuit configured to enable the sense amplifier during a time period, and a second circuit configured to enable the write driver during at least a portion of the time period. The method includes enabling a sense amplifier to sense read data from a memory cell during a time period and enabling a write driver to provide write data to the memory cell during at least a portion of the time period. Another memory and method for operating the memory are presented. The memory and method further include an address input circuit configured to receive a write address while the sense amplifier is enabled.

公开(公告)号：US09154117B2

公开(公告)日：2015-10-06

申请号：US13787530

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Nishith Desai ,  Rakesh Vattikonda

IPC: H03K3/00 ,  H03K3/356

CPC classification number: H03K3/356104

Abstract: Various apparatuses and methods are disclosed. The system describes a pulse generator comprising a first stage configured to be powered by a first voltage; and a second stage configured to be powered by a second voltage different from the first voltage, wherein the second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage.

Abstract translation: 公开了各种装置和方法。 该系统描述了脉冲发生器，其包括被配置为由第一电压供电的第一级; 以及第二级，其被配置为由不同于所述第一电压的第二电压供电，其中所述第二级还被配置为响应于包括来自所述第二级的触发和来自所述第一级的输入而产生脉冲。

公开(公告)号：US09036446B2

公开(公告)日：2015-05-19

申请号：US13663042

申请日：2012-10-29

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar ,  Balachander Ganesan ,  Alex Dongkyu Park

IPC: G11C8/00 ,  G11C8/10

CPC classification number: G11C8/10

Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

Abstract translation: 一种用于存储器中基于脉冲锁存器的预解码器的全局复位产生方法，包括产生用于脉冲锁存电路的预解码存储器地址输出，产生复位信号以复位脉冲锁存电路，提供预处理器的组合信号， 解码的存储器地址输出和复位信号，将组合的信号馈送到低电压阈值器件以操纵复位脉冲锁存电路，其中产生复位信号包括产生来自匹配电路的复位信号，该匹配电路被配置为模拟 锁存电路被复位并且其中产生复位信号包括配置匹配电路以适应最坏情况保持脉冲延迟，以允许在新的时钟周期执行复位之前复位脉冲锁存器并使匹配电路提供复位信号和 在同一电压域内预编译的存储器地址输出。

公开(公告)号：US20140219039A1

公开(公告)日：2014-08-07

申请号：US13760988

申请日：2013-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： Changho Jung ,  Nishith Desai ,  Rakesh Vattikonda

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/00 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/419

Abstract: A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMlower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP≧VddM>VddMlower.

Abstract translation: 提供一种写辅助驱动器电路，即使当电源电压降低时，也可以在写入操作中帮助存储器单元（例如，易失性存储器位单元）来保持存储器核心处的电压足够高以用于正确的写入操作。 写辅助驱动器电路可以被配置为在待机操作模式期间向位单元核提供存储器电源电压VddM。 在写入操作模式中，写入辅助驱动器电路可以向位单元核心以及本地写入位线（lwbl）和本地写入位线条（lwblb）中的至少一个提供降低的存储器电源电压VddMlower。 此外，写辅助驱动器电路还可以向本地写入字线（lww1）提供外围电源电压VddP，其中VddP≥VddM> VddMlower。

公开(公告)号：US12014771B2

公开(公告)日：2024-06-18

申请号：US18175023

申请日：2023-02-27

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Arun Babu Pallerla ,  Chulmin Jung

IPC: G11C11/419 ,  G11C11/413 ,  H03K19/20

CPC classification number: G11C11/419 ,  G11C11/413 ,  H03K19/20

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.