公开(公告)号：US20170083827A1

公开(公告)日：2017-03-23

申请号：US14862408

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Behnam Robatmili ,  Matthew Leslie Badin ,  Dario Suárez Gracia ,  Gheorghe Calin Cascaval ,  Nayeem Islam

IPC: G06N99/00

CPC classification number: G06N20/00 ,  G06F15/8092

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for accelerating machine learning on a computing device. Raw data may be received in the computing device from a raw data source device. The apparatus may identify key features as two dimensional matrices of the raw data such that the key features are mutually exclusive from each other. The key features may be translated into key feature vectors. The computing device may generate a feature vector from at least one of the key feature vectors. The computing device may receive a first partial output resulting from an execution of a basic linear algebra subprogram (BLAS) operation using the feature vector and a weight factor. The first partial output may be combined with a plurality of partial outputs to produce an output matrix. Receiving the raw data on the computing device may include receiving streaming raw data.

公开(公告)号：US09501328B2

公开(公告)日：2016-11-22

申请号：US14673857

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Behnam Robatmili ,  Shaizeen Dilawarhusen Aga ,  Dario Suarez Gracia ,  Arun Raman ,  Aravind Natarajan ,  Gheorghe Calin Cascaval ,  Pablo Montesinos Ortego ,  Han Zhao

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5066 ,  G06F9/5027

Abstract: Embodiments include computing devices, systems, and methods for task-based handling of repetitive processes in parallel. At least one processor of the computing device, or a specialized hardware controller, may be configured to partition iterations of a repetitive process and assign the partitions to initialized tasks to be executed in parallel by a plurality of processor cores. Upon completing a task, remaining divisible partitions of the repetitive process of ongoing tasks may be subpartitioned and assigned to the ongoing task, and the completed task or a newly initialized task. Information about the iteration space for a repetitive process may be stored in a descriptor table, and status information for all partitions of a repetitive process stored in a status table. Each processor core may have an associated local table that tracks iteration execution of each task, and is synchronized with the status table.

Abstract translation: 实施例包括用于并行地重复处理的基于任务的处理的计算设备，系统和方法。 计算设备的至少一个处理器或专用硬件控制器可以被配置为分区重复过程的迭代，并且将分区分配给由多个处理器核并行执行的初始化任务。 完成任务后，正在执行的任务的重复进程的剩余可分区可以被分分区并分配给正在进行的任务，以及完成的任务或新初始化的任务。 关于重复过程的迭代空间的信息可以存储在描述符表中，以及存储在状态表中的重复进程的所有分区的状态信息。 每个处理器核心可以具有跟踪每个任务的迭代执行的相关联的本地表，并且与状态表同步。

公开(公告)号：US20160291981A1

公开(公告)日：2016-10-06

申请号：US14679408

申请日：2015-04-06

Applicant: QUALCOMM Incorporated

Inventor： Behnam Robatmili ,  Gheorghe Calin Cascaval ,  Michael William Morrow ,  Derek Jay Conrod ,  Bohuslav Rychlik

IPC: G06F9/38

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3832

Abstract: Removing invalid literal load values, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a literal load table containing one or more entries comprising an address and a cached literal load value. Upon detecting a literal load instruction in an instruction stream, the instruction processing circuit determines whether the literal load table contains an entry having an address of the literal load instruction. If so, the instruction processing circuit removes the literal load instruction from the instruction stream, and provides the cached literal load value stored in the entry to at least one dependent instruction. The instruction processing circuit further determines whether an invalidity indicator for the literal load table has been received. If so, the instruction processing circuit flushes the literal load table. The invalidity indicator may be generated responsive to modification of a constant table.

Abstract translation: 公开了删除无效文字负载值以及相关电路，方法和计算机可读介质。 在一个方面，指令处理电路提供包含一个或多个条目的文字加载表，该条目包括地址和缓存的字面负载值。 在指令流中检测到文字加载指令时，指令处理电路确定文字加载表是否包含具有文字加载指令地址的条目。 如果是这样，则指令处理电路从指令流中去除文字加载指令，并将存储在该条目中的缓存的文字加载值提供给至少一个从属指令。 指令处理电路还确定是否已经接收到文字负载表的无效指示符。 如果是这样，指令处理电路刷新文字负载表。 可以响应于常数表的修改来生成无效指示符。

公开(公告)号：US20160277435A1

公开(公告)日：2016-09-22

申请号：US14661195

申请日：2015-03-18

Applicant: QUALCOMM Incorporated

Inventor： Mastooreh Salajegheh ,  Mona Mahmoundi ,  Vinay Sridhara ,  Mihai Christodorescu ,  Gheorghe Calin Cascaval

IPC: H04L29/06

CPC classification number: H04L63/1441 ,  G06F9/46 ,  G06F11/3409 ,  G06F21/552 ,  G06F21/6254 ,  H04L63/0421 ,  H04L63/1416 ,  H04L63/1425 ,  H04W12/02 ,  H04W12/12 ,  H04W24/10

Abstract: Methods, and devices implementing the methods, use device-specific classifiers in a privacy-preserving behavioral monitoring and analysis system for crowd-sourcing of device behaviors. Diverse devices having varying degrees of “smart” capabilities may monitor operational behaviors. Gathered operational behavior information may be transmitted to a nearby device having greater processing capabilities than a respective collecting device, or may be transmitted directly to an “always on” device. The behavior information may be used to generate behavior vectors, which may be analyzed for anomalies. Vectors containing anomaly flags may be anonymized to remove any user-identifying information and subsequently transmitted to a remote recipient such as a service provider or device manufacture. In this manner, operational behavior information may be gathered about different devices from a large number of users, to obtain statistical analysis of operational behavior for specific makes and models of devices, without divulging personal information about device users.

Abstract translation: 方法和实现方法的设备在隐私保护行为监控和分析系统中使用设备特定的分类器，用于人群来源的设备行为。 具有不同程度的“智能”能力的不同装置可以监视操作行为。 聚集的操作行为信息可以被发送到具有比相应的收集装置更大的处理能力的附近设备，或者可以直接传送到“始终处于”设备。 行为信息可用于生成行为矢量，可以对异常进行分析。 可以对包含异常标志的向量进行匿名处理，以消除任何用户识别信息，并随后发送到诸如服务提供商或设备制造的远程接收者。 以这种方式，可以从大量用户收集关于不同设备的操作行为信息，以获得关于特定设备和型号的操作行为的统计分析，而不泄漏关于设备用户的个人信息。

公开(公告)号：US20150355700A1

公开(公告)日：2015-12-10

申请号：US14300457

申请日：2014-06-10

Applicant: QUALCOMM Incorporated

Inventor： Kishore Kumar Pusukuri ,  Gheorghe Calin Cascaval ,  Michael Weber

IPC: G06F1/32 ,  G06F1/08 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/4893 ,  G06F9/5011 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

Abstract: The aspects include systems and methods of managing processor device power consumption. A processor may determine a thread execution metric for each of a plurality of threads scheduled for execution in a processor comprising a plurality of processing cores. The processor may allocate to a selected processing core or cores those threads whose thread execution metric satisfies a threshold. The processor may reduce a frequency of the selected processing core or cores to reduce the power consumption.

Abstract translation: 这些方面包括管理处理器设备功耗的系统和方法。 处理器可以为调度用于在包括多个处理核心的处理器中执行的多个线程中的每一个确定线程执行度量。 处理器可以分配给所选择的处理核心或者核心其线程执行度量满足阈值的那些线程。 处理器可以降低所选择的处理核心或核心的频率以减少功耗。

公开(公告)号：US20150286565A1

公开(公告)日：2015-10-08

申请号：US14744831

申请日：2015-06-19

Applicant: QUALCOMM INCORPORATED

Inventor： Subrato K. De ,  Richard A. Stewart ,  Gheorghe Calin Cascaval ,  Dexter T. Chun

IPC: G06F12/02 ,  G11C7/10

CPC classification number: G06F12/023 ,  G06F12/0607 ,  G06F12/0638 ,  G06F2212/1044 ,  G11C7/1072 ,  Y02D10/13

Abstract: Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).

Abstract translation: 提供了系统和方法，用于将存储器分配给不同的存储器件。 示例性实施例包括用于将不同的存储器件分配存储器的方法。 确定交织带宽比，其包括两个或多个不同存储器件的带宽比。 不同的存储器件根据交织带宽比进行交织以定义具有不同性能级别的两个或多个存储器区域。 基于服务质量（QoS）将内存地址请求分配给内存区域。

公开(公告)号：US20150205726A1

公开(公告)日：2015-07-23

申请号：US14262852

申请日：2014-04-28

Applicant: QUALCOMM Incorporated

Inventor： Behnam Robatmili ,  Gheorghe Calin Cascaval ,  Madhukar Nagaraja Kedlaya ,  Dario Suarez Gracia

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/4491 ,  G06F12/0802 ,  G06F2212/452

Abstract: Aspects include a computing devices, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.

Abstract translation: 方面包括用于动态语言的内联高速缓存的硬件加速的计算设备，系统和方法。 可以为动态软件操作的实例初始化内联缓存。 动态软件操作的初始化实例的调用可以由内联高速缓存硬件加速器执行。 可以检查内联高速缓存以确定其数据是当前的。 当数据是最新的时，可以使用相关的在线高速缓存数据来执行动态软件操作的初始化实例。 当数据不是当前的时候，可以为动态软件操作的实例初始化新的内联高速缓存，包括动态软件操作的先前初始化的实例的当前数据。 内联高速缓存硬件加速器可以包括内联高速缓冲存储器，协处理器和/或功能，直到连接到处理器流水线的内联高速缓存流水线为止。