公开(公告)号：US20240429908A1

公开(公告)日：2024-12-26

申请号：US18340449

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Harshat PANT ,  Hanil LEE ,  Shih-Hsin Jason HU ,  Chulmin JUNG ,  Xiao CHEN ,  Christol BARNES

IPC: H03K17/00 ,  G05F1/46

Abstract: A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

公开(公告)号：US20240355381A1

公开(公告)日：2024-10-24

申请号：US18306167

申请日：2023-04-24

Applicant: QUALCOMM Incorporated

Inventor： Seohee KIM ,  Chulmin JUNG ,  Xiao CHEN ,  Hanil LEE ,  Venugopal BOYNAPALLI ,  Jung Pill KIM

IPC: G11C11/413 ,  H03K5/24 ,  H10B10/00

CPC classification number: G11C11/413 ,  H03K5/24 ,  H10B10/18

Abstract: An integrated circuit is disclosed that includes a power supply multiplexer for selecting between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage to a memory. A controller includes a comparator stage having a comparator with switchable inputs so that the comparator stage may control a binary state of a first output signal responsive to whether the first power supply voltage is greater than the second power supply voltage plus a voltage offset of the comparator. Similarly, the comparator stage may control a binary state of a second output signal responsive to whether the first power supply voltage is greater than the second power supply voltage minus the voltage offset. The controller controls the selection by the power supply multiplexer responsive to the binary states of the first and second output signals.

公开(公告)号：US20230139283A1

公开(公告)日：2023-05-04

申请号：US17517386

申请日：2021-11-02

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Chulmin JUNG

IPC: G11C29/50 ,  G11C8/08

Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

公开(公告)号：US20230087277A1

公开(公告)日：2023-03-23

申请号：US17481601

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hochul LEE ,  Anil Chowdary KOTA ,  Dhvani SHETH ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

公开(公告)号：US20220068360A1

公开(公告)日：2022-03-03

申请号：US17002082

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG ,  Sung SON ,  Jason CHENG ,  Yandong GAO ,  Chulmin JUNG ,  Venugopal BOYNAPALLI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/02

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

公开(公告)号：US20210255243A1

公开(公告)日：2021-08-19

申请号：US16794105

申请日：2020-02-18

Applicant: QUALCOMM Incorporated

Inventor： Sonia GHOSH ,  Changho JUNG ,  Chulmin JUNG

IPC: G01R31/3181 ,  G01J1/18 ,  G01R31/317

Abstract: According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.

公开(公告)号：US20210098057A1

公开(公告)日：2021-04-01

申请号：US16911313

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Chulmin JUNG ,  Percy DADABHOY

IPC: G11C11/419 ,  H03K3/3562 ,  H04M1/02

Abstract: A memory is provided with a pre-charge circuit/write driver that pre-charges a bit line in a bit line pair responsive to a master latch output signal from a master latch in a data buffer. A slave latch associated with the master latch is prevented from becoming open by a clock controller during write operations for the memory.

公开(公告)号：US20200133862A1

公开(公告)日：2020-04-30

申请号：US16173221

申请日：2018-10-29

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar RANGARAJAN ,  Chulmin JUNG ,  Rakesh MISRA

IPC: G06F12/0846 ,  G06F12/0808 ,  G06F12/0891 ,  G06F12/0895

Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.