公开(公告)号：US20140119102A1

公开(公告)日：2014-05-01

申请号：US13787875

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Harish Shankar ,  David Paul Hoff ,  Manish Garg

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C8/08 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers. When a simultaneous read and write operation to a first entry of the memory array is detected, the read operation to the first entry is suppressed and a dummy read operation to a second entry of the memory array is performed. The write operation to the first entry is allowed to proceed undisturbed.

Abstract translation: 用于检测和抑制存储器阵列中的电涌电流的系统和方法。 在具有交叉耦合的位线保持器的静态随机存取存储器（SRAM）阵列中，实现了虚拟读取以防止在同时读写冲突的情况下的撬棒电流。 当检测到对存储器阵列的第一条目的同时读取和写入操作时，对第一条目的读取操作被抑制，并且执行对存储器阵列的第二条目的伪读取操作。 允许对第一个条目的写入操作不受干扰。

公开(公告)号：US12265711B1

公开(公告)日：2025-04-01

申请号：US18412776

申请日：2024-01-15

Applicant: QUALCOMM Incorporated

Inventor： Ashwini Pandey ,  Pratibind Kumar Jha ,  Manish Garg

IPC: G06F3/06

Abstract: Methods that may be performed by a universal flash storage (UFS) device of a computing device for configuring flash memory cells. Various embodiments may include setting a number of degraded triple-level cells (TLCs) attribute, and configuring at least one degraded TLC as at least one single-level cell (SLC) based on the number of degraded TLCs attribute, the at least one degraded TLC being not functional as a TLC and functional as an SLC. Some embodiments may include identifying the at least one degraded TLC based on at least one degradation attribute associated with the at least one degraded TLC, the at least one degradation attribute configured to indicate that the at least one degraded TLC is not functional as a TLC, and identifying an amount of degraded TLCs that are not functional as a TLC.

公开(公告)号：US20180121274A1

公开(公告)日：2018-05-03

申请号：US15642451

申请日：2017-07-06

Applicant: QUALCOMM Incorporated

Inventor： Thomas Philip Speier ,  Viren Ramesh Patel ,  Michael Phan ,  Manish Garg ,  Kevin Magill ,  Paul Steinmetz ,  Clint Mumford ,  Kshitiz Saxena

IPC: G06F11/07 ,  G06F12/0891 ,  G06F9/44

CPC classification number: G11C29/44 ,  G06F11/073 ,  G06F11/0787 ,  G11C29/76 ,  G11C29/789 ,  G11C29/824 ,  G11C29/832 ,  G11C29/84 ,  G11C29/883 ,  G11C2029/0401 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.

公开(公告)号：US20160240244A1

公开(公告)日：2016-08-18

申请号：US14857512

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  Manish Garg ,  Joshua Lance Puckett ,  Rahul Krishnakumar Nadkarni

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16

Abstract: Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.

Abstract translation: 公开了用于在字线激活之后检测存储器系统中的读写冲突的冲突检测系统。 一方面，提供了一种碰撞检测系统。 碰撞检测系统包括用于存储器阵列的每个比特单元行的冲突检测电路。 每个碰撞检测电路被配置为接收对应于位单元行的写入和读取字线信号。 冲突检测电路被配置为检测对同一位单元行的写入和读取操作有效的写入和读取字线信号对。 冲突检测电路被配置为产生冲突检测信号，以通知与存储器系统相关联的客户发生读写冲突。 在读取字线激活之后检测读写冲突减少或避免读取路径中的开销延迟，而不是在激活读取字线之前检测读写冲突。