公开(公告)号：US10156887B2

公开(公告)日：2018-12-18

申请号：US15280328

申请日：2016-09-29

Applicant: QUALCOMM Incorporated

Inventor： Michael Phan

IPC: G06F1/32 ,  G06F12/0864 ,  G06F1/08 ,  G06F12/0895 ,  G11C8/18

Abstract: Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and generate a one way hit signal indicating if cache read request results in a single way hit. Clock and enable circuit is configured to generate a cache clock signal in response to a system clock signal and a cache enable signal, and generate a cache read enable signal in response to the cache clock signal and a read enable signal. Gating circuit is configured to generate a read clock signal in response to one way hit signal, cache clock signal, and cache read enable signal. Sense amplifier clock generation circuit is configured to generate sense amplifier clock signal in response to the read clock signal having a defined pulse width.

公开(公告)号：US10541044B2

公开(公告)日：2020-01-21

申请号：US15642451

申请日：2017-07-06

Applicant: QUALCOMM Incorporated

Inventor： Thomas Philip Speier ,  Viren Ramesh Patel ,  Michael Phan ,  Manish Garg ,  Kevin Magill ,  Paul Steinmetz ,  Clint Mumford ,  Kshitiz Saxena

IPC: G11C29/44 ,  G06F11/07 ,  G11C29/00

Abstract: Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.

公开(公告)号：US20180121274A1

公开(公告)日：2018-05-03

申请号：US15642451

申请日：2017-07-06

Applicant: QUALCOMM Incorporated

Inventor： Thomas Philip Speier ,  Viren Ramesh Patel ,  Michael Phan ,  Manish Garg ,  Kevin Magill ,  Paul Steinmetz ,  Clint Mumford ,  Kshitiz Saxena

IPC: G06F11/07 ,  G06F12/0891 ,  G06F9/44

CPC classification number: G11C29/44 ,  G06F11/073 ,  G06F11/0787 ,  G11C29/76 ,  G11C29/789 ,  G11C29/824 ,  G11C29/832 ,  G11C29/84 ,  G11C29/883 ,  G11C2029/0401 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.

公开(公告)号：US10559352B2

公开(公告)日：2020-02-11

申请号：US16134937

申请日：2018-09-18

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  Manish Garg ,  Rahul Krishnakumar Nadkarni ,  Rajesh Kumar ,  Michael Phan

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/08 ,  G11C8/18 ,  G11C7/10 ,  G11C11/418

Abstract: A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

公开(公告)号：US20180088659A1

公开(公告)日：2018-03-29

申请号：US15280328

申请日：2016-09-29

Applicant: QUALCOMM Incorporated

Inventor： Michael Phan

IPC: G06F1/32 ,  G06F12/0864 ,  G06F1/08

CPC classification number: G06F1/3275 ,  G06F1/08 ,  G06F1/324 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  G11C8/18 ,  Y02D10/13

Abstract: Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and generate a one way hit signal indicating if cache read request results in a single way hit. Clock and enable circuit is configured to generate a cache clock signal in response to a system clock signal and a cache enable signal, and generate a cache read enable signal in response to the cache clock signal and a read enable signal. Gating circuit is configured to generate a read clock signal in response to one way hit signal, cache clock signal, and cache read enable signal. Sense amplifier clock generation circuit is configured to generate sense amplifier clock signal in response to the read clock signal having a defined pulse width.