公开(公告)号：US20160329330A1

公开(公告)日：2016-11-10

申请号：US15216856

申请日：2016-07-22

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA ,  Satoshi IIDA

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract translation: 本发明提供一种半导体集成电路器件的制造方法，其包括在其侧表面上形成硬掩模膜，其中的开口和侧壁绝缘膜; 在所述开口中形成浅沟槽，所述硬掩模膜作为掩模，并至少氧化暴露部分; 用绝缘膜填充沟槽，然后将其移除，使其离开开口中的沟槽，从而在沟槽内部和外部形成漏极偏移STI绝缘膜; 以及形成从栅极绝缘膜的上部延伸的栅极电极与其邻接的有源区域延伸到漏极绝缘膜的上部。

公开(公告)号：US20160293427A1

公开(公告)日：2016-10-06

申请号：US15043579

申请日：2016-02-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA ,  Masaaki SHINOHARA

IPC: H01L21/28 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, a first insulation film, a conductive film, a silicon-containing second insulation film, and a third film formed of silicon are sequentially formed at the surface of a control gate electrode. Then, the third film is etched back to leave the third film at the side surface of the control gate electrode via the first insulation film, the conductive film, and the second insulation film, thereby to form a spacer. Then, the conductive film is etched back to form a memory gate electrode formed of the conductive film between the spacer and the control gate electrode, and between the spacer and the semiconductor substrate.

Abstract translation: 提高了半导体器件的性能。 在半导体器件的制造方法中，在控制栅电极的表面依次形成第一绝缘膜，导电膜，含硅第二绝缘膜和由硅形成的第三膜。 然后，通过第一绝缘膜，导电膜和第二绝缘膜将第三膜蚀刻回留在控制栅电极的侧表面处，从而形成间隔物。 然后，将导电膜回蚀以形成由间隔物和控制栅电极之间以及间隔物与半导体衬底之间的导电膜形成的存储栅电极。

公开(公告)号：US20140227839A1

公开(公告)日：2014-08-14

申请号：US14085825

申请日：2013-11-21

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA

IPC: H01L27/11

CPC classification number: H01L21/28282 ,  H01L21/3212 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.

Abstract translation: 提供了具有改进的性能的半导体器件。 在位于存储单元区域中的半导体衬底中，形成非易失性存储器的存储单元，同时形成位于外围电路区域中的半导体衬底中的MISFET。 此时，首先在位于存储单元区域的半导体基板上形成各自用于存储单元的控制栅电极和存储栅电极。 然后，形成绝缘膜以覆盖控制栅电极和存储栅电极。 随后，绝缘膜的上表面被抛光以平坦化。 此后，形成用于MISFET的栅电极的导电膜，然后将其图案化以在外围电路区域中形成用于MISFET的栅电极或伪栅电极。