公开(公告)号：US20200005353A1

公开(公告)日：2020-01-02

申请号：US16447391

申请日：2019-06-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya SHIBAYAMA ,  Seiji MOCHIZUKI ,  Nhat Van HUYNH ,  Hiroshi UEDA ,  Toshiyuki KAYA

IPC: G06Q30/02

Abstract: The present invention provides a service car in which the effect of advertisement is increased and the convenience for users is increased.The processing executed by the CPU of the moving object as the service car includes the steps of obtaining an advertisement from the server (S505), displaying the advertisement on a monitor outside the moving object (S510), accepting input of each signal output from an external information acquisition device (camera, microphone, sensor) provided in the moving object (S520), obtaining external information representing the periphery of the moving object and storing the information (S530), obtaining the travel information of the moving object (S540), estimating the effect of the advertisement based on the external information and the travel information (S550), determining a reward for the advertisement based on a predetermined reward criterion and the effect (S560), and calculating a usage fee for the moving object based on the determined reward.

公开(公告)号：US20180184080A1

公开(公告)日：2018-06-28

申请号：US15798160

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Toshiyuki KAYA ,  Seiji MOCHIZUKI ,  Katsushige MATSUBARA ,  Ryoji HASHIMOTO ,  Ren IMAOKA

IPC: H04N17/00 ,  H04N5/232 ,  H04N17/02

CPC classification number: H04N17/004 ,  G06F3/14 ,  G06T1/20 ,  G09G3/2037 ,  G09G2330/10 ,  G09G2330/12 ,  G09G2340/02 ,  H04N1/32283 ,  H04N5/23293 ,  H04N9/045 ,  H04N17/02 ,  H04N19/89 ,  H04N2209/042

Abstract: An object of the present invention is to detect a failure of a camera input in a system including a camera or a video transmission path (camera input). An image processor includes a hash derivation circuit having a computing unit that calculates hash values on an input screen and a storage circuit that stores the hash values. The image processor compares the hash values between multiple frames so as to decide whether the screens have changed or stopped. A failure is detected when the screens are stopped.

公开(公告)号：US20180150428A1

公开(公告)日：2018-05-31

申请号：US15884576

申请日：2018-01-31

Applicant: Renesas Electronics Corporation

Inventor： Takahiko SUGIMOTO ,  Tomohiro UNE ,  Hiroshi UEDA ,  Ryoji HASHIMOTO ,  Toshiyuki KAYA

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4221 ,  G06F13/00 ,  G06F13/4009 ,  G06F13/4027

Abstract: A data processing device includes a data selector circuit that divides a plurality of types of data into another plurality of types of data in accordance with a classification of the data, a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data, and a data transmission circuit that transmits the plurality of types of compressed data to a terminal.

公开(公告)号：US20170017591A1

公开(公告)日：2017-01-19

申请号：US15144561

申请日：2016-05-02

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi UEDA ,  Ren IMAOKA ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA

IPC: G06F13/28 ,  H04N19/436 ,  H04N19/423 ,  H04N19/184 ,  H04N19/169

CPC classification number: G06F13/28 ,  H04N19/184 ,  H04N19/188 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436

Abstract: A data processing system includes a plurality of data processing devices that perform in parallel data processing on the basis of initial setup data. The data processing devices each has a unique ID and includes a plurality of registers that store the initial setup data and a transfer circuit. The transfer circuit receives packets including a payload that is the initial setup data, shared information, a destination ID and a destination address and, when the shared information indicates that the payload is the initial setup data to be set commonly into the plurality of the data processing devices including its own data processing device, transfers the payload to the register that the destination address indicates irrespective of mismatching between the destination ID and its own ID.

Abstract translation: 数据处理系统包括基于初始设置数据执行并行数据处理的多个数据处理设备。 数据处理装置各自具有唯一的ID，并且包括存储初始建立数据的多个寄存器和传送电路。 传输电路接收包括作为初始设置数据，共享信息，目的地ID和目的地地址的有效载荷的分组，并且当共享信息指示有效负载是要被共同设置到多个数据中的初始设置数据时 包括其自己的数据处理设备的处理设备将目的地地址指示的有效载荷传送到目的地ID与其自己的ID之间的不匹配。

公开(公告)号：US20160227236A1

公开(公告)日：2016-08-04

申请号：US14970603

申请日：2015-12-16

Applicant: Renesas Electronics Corporation

Inventor： Keisuke MATSUMOTO ,  Katsushige MATSUBARA ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Hiroshi UEDA

IPC: H04N19/423 ,  H04N19/51 ,  H04N19/593 ,  H04N19/136 ,  H04N19/65 ,  H04N19/176 ,  H04N19/44 ,  H04N19/127

CPC classification number: H04N19/423 ,  H04N19/127 ,  H04N19/136 ,  H04N19/139 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176 ,  H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/593 ,  H04N19/65

Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.

Abstract translation: 在图像处理装置中，运动图像解码处理部根据输入流提取要解码的目标图像的特征量，并根据特征将高速缓存填充的读取大小从外部存储器改变为高速缓冲存储器 量。 特征量表示例如一个图像（帧或场）或运动矢量变化中的宏块内比例。 当宏块内比例高时，缓存填充的读取大小减小。

公开(公告)号：US20160198174A1

公开(公告)日：2016-07-07

申请号：US14928735

申请日：2015-10-30

Applicant: Renesas Electronics Corporation

Inventor： Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Hiroshi UEDA ,  Tetsuya SHIBAYAMA

IPC: H04N19/46 ,  H04N19/44 ,  H04N19/89 ,  H04N19/423

CPC classification number: H04N19/46 ,  H04N17/004 ,  H04N19/44 ,  H04N19/65 ,  H04N19/89

Abstract: A video encoding/decoding system includes a video encoding device and a video decoding device. The video encoding device includes an encoding part for encoding a diagnostic image or normal image. The video decoding device includes a decoding part for decoding the image encoded by the encoding part, a check signal generation part for generating a check signal of the decoded image, a storage part for storing the expected value of the check signal of the diagnostic image or the check signal generated by the check signal generation part, and a comparison part for comparing the check signal stored in the storage part with the check signal generated by the check signal generation part, in order to detect failure in all the paths from the image input part of the video encoding device to the image output part of the video decoding device.

Abstract translation: 视频编码/解码系统包括视频编码装置和视频解码装置。 视频编码装置包括用于对诊断图像或正常图像进行编码的编码部分。 视频解码装置包括用于对由编码部分编码的图像进行解码的解码部分，用于产生解码图像的检查信号的检查信号产生部分，用于存储诊断图像的检查信号的期望值的存储部分或 由检查信号生成部生成的检查信号，以及比较部，其将存储在存储部中的检查信号与由检查信号生成部生成的检查信号进行比较，以检测从图像输入的所有路径中的故障 视频编码装置的一部分到视频解码装置的图像输出部分。

公开(公告)号：US20160007025A1

公开(公告)日：2016-01-07

申请号：US14749505

申请日：2015-06-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiyuki KAYA ,  Seiji MOCHIZUKI ,  Tetsuya SHIBAYAMA ,  Kenichi IWATA ,  Hiroshi UEDA ,  Ren IMAOKA

IPC: H04N19/159 ,  H04N19/176 ,  H04N19/12

CPC classification number: H04N19/159 ,  H04N19/105 ,  H04N19/12 ,  H04N19/16 ,  H04N19/176 ,  H04N19/433 ,  H04N19/436 ,  H04N19/597

Abstract: In a picture encoding device and a picture decoding device, the access to a reference frame memory is suppressed. The picture encoding device is comprised of a first encoder for intra picture encoding, a second encoder for inter picture encoding, and an intermediate buffer. A local decoded picture generated by the first encoder is stored as a reference picture in the intermediate buffer, and the inter picture encoding by the second encoder is performed by referring to the local decoded picture in the intermediate buffer. A picture decoding device is comprised of a first decoder for intra picture decoding, a second decoder for inter picture decoding, and an intermediate buffer. A local decoded picture generated by the first decoder is stored as a reference picture in the intermediate buffer, and the inter picture decoding by the second decoder is performed by referring the local decoded picture in the intermediate buffer.

Abstract translation: 在图像编码装置和图像解码装置中，抑制对基准帧存储器的访问。 图像编码装置包括用于画面内编码的第一编码器，用于帧间编码的第二编码器和中间缓冲器。 由第一编码器产生的局部解码图像作为参考图像存储在中间缓冲器中，并且通过参考中间缓冲器中的局部解码图像来执行由第二编码器进行的帧间编码。 图像解码装置包括用于画面内解码的第一解码器，用于画面间解码的第二解码器和中间缓冲器。 由第一解码器产生的局部解码图像作为参考图像存储在中间缓冲器中，并且通过参考中间缓冲器中的局部解码图像来执行第二解码器的帧间图像解码。

公开(公告)号：US20150117549A1

公开(公告)日：2015-04-30

申请号：US14518110

申请日：2014-10-20

Applicant: Renesas Electronics Corporation

Inventor： Katsushige MATSUBARA ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Tetsuya SHIBAYAMA

IPC: H04N19/44

CPC classification number: H04N19/436 ,  H04N19/44

Abstract: The present invention is directed to reduce deterioration in parallel processing capability. In a moving-picture decoding processing apparatus, information of a first plurality of frames and a second plurality of frames is supplied from a decoding control unit to first and second decoding processing units. For decoding the information from an intermediate point to an end point of a second preceding frame by the second decoding unit in a third period, use of a result of the process of the first decoding processing unit in the third period is inhibited, and use of a result of the process of a first preceding frame by the first decoding processing unit in a second period is permitted by an end signal. By reach of the intermediate point of the decoding of the second preceding frame by the second decoding processing unit in the second period, information from the start point to the intermediate point of the first subsequent frame included in the plural frames is decoded by the first decoding unit in the third period.

Abstract translation: 本发明旨在减少并行处理能力的恶化。 在运动图像解码处理装置中，将第一多个帧和第二多个帧的信息从解码控制单元提供给第一和第二解码处理单元。 为了在第三时段中由第二解码单元从第二前一帧的中间点到终点的信息解码，禁止在第三周期中使用第一解码处理单元的处理结果，并且使用 结束信号允许由第一解码处理单元在第二时段中的第一前一帧的处理结果。 在第二时段中，通过第二解码处理单元对第二前一帧的解码的中间点的到达，通过第一解码对来自包含在多个帧中的第一后续帧的起始点到中间点的信息进行解码 单位在第三期。