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公开(公告)号:US20190095324A1
公开(公告)日:2019-03-28
申请号:US16057713
申请日:2018-08-07
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Keisuke MATSUMOTO , Seiji MOCHIZUKI , Hiroshi UEDA , Katsushige MATSUBARA
Abstract: Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.
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公开(公告)号:US20180253127A1
公开(公告)日:2018-09-06
申请号:US15858361
申请日:2017-12-29
Applicant: Renesas Electronics Corporation
Inventor: Hiroshi UEDA , Ryoji HASHIMOTO , Taku MAEKAWA , Katsushige MATSUBARA , Keisuke MATSUMOTO
Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
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3.
公开(公告)号:US20170039160A1
公开(公告)日:2017-02-09
申请号:US14915621
申请日:2015-03-12
Applicant: Renesas Electronics Corporation
Inventor: Takahiko SUGIMOTO , Tomohiro UNE , Hiroshi UEDA , Ryoji HASHIMOTO , Toshiyuki KAYA
CPC classification number: G06F13/4221 , G06F13/00 , G06F13/4009 , G06F13/4027
Abstract: A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal.
Abstract translation: 数据选择器电路将包括多种类型的数据的数据组划分成多种类型的数据。 第一压缩电路和第二压缩电路根据多种类型的数据分别彼此并行地压缩多种类型的数据。 第一压缩电路压缩数据并获得压缩数据。 第二压缩电路压缩数据并获得压缩数据。 数据传输电路将压缩数据和压缩数据发送到终端。
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公开(公告)号:US20160283430A1
公开(公告)日:2016-09-29
申请号:US14965612
申请日:2015-12-10
Applicant: Renesas Electronics Corporation
Inventor: Hiroshi UEDA , Seiji MOCHIZUKI , Toshiyuki KAYA , Kenichi IWATA , Katsushige MATSUBARA
CPC classification number: G06F13/4068 , G06F9/5066 , G06F13/28 , H04N19/176 , H04N19/423 , H04N19/436
Abstract: A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).
Abstract translation: 提供在处理单元之间传送数据的多个传送模块(402-0至402-M),以分别对应于多个处理单元(401-0至401-M)。 对于每个处理单元(401-0至401-M),第一环形总线(403-0至403-M)连接相应处理单元内的子单元和对应于处理单元的传送模块,从而形成 环形。 多个传送模块(402-0至402-M)被连接成使得它们通过第二环形总线(404)形成环形。
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公开(公告)号:US20240331080A1
公开(公告)日:2024-10-03
申请号:US18589997
申请日:2024-02-28
Applicant: Renesas Electronics Corporation
Inventor: Hiroshi UEDA , Ryoji HASHIMOTO , Kaito MORI
IPC: G06T1/20
CPC classification number: G06T1/20
Abstract: The video data processing device includes at least one first functional module that performs first processing preset for each first processing unit data, at least one second functional module that performs second processing preset for each second processing unit data smaller than the first processing unit data, and a control unit that controls the execution order of pipeline processing for the first processing unit data by controlling the timing at which the first function module and the second function module operate. The control unit controls the subsequent stage so that the first function module and the second module are started in response to the completion of the respective processing in accordance with the end of the pre-stage.
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公开(公告)号:US20200233471A1
公开(公告)日:2020-07-23
申请号:US16842399
申请日:2020-04-07
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Hiroshi UEDA , Ryoji HASHIMOTO , Taku MAEKAWA , Katsushige MATSUBARA , Keisuke MATSUMOTO
Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
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7.
公开(公告)号:US20200005353A1
公开(公告)日:2020-01-02
申请号:US16447391
申请日:2019-06-20
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Tetsuya SHIBAYAMA , Seiji MOCHIZUKI , Nhat Van HUYNH , Hiroshi UEDA , Toshiyuki KAYA
IPC: G06Q30/02
Abstract: The present invention provides a service car in which the effect of advertisement is increased and the convenience for users is increased.The processing executed by the CPU of the moving object as the service car includes the steps of obtaining an advertisement from the server (S505), displaying the advertisement on a monitor outside the moving object (S510), accepting input of each signal output from an external information acquisition device (camera, microphone, sensor) provided in the moving object (S520), obtaining external information representing the periphery of the moving object and storing the information (S530), obtaining the travel information of the moving object (S540), estimating the effect of the advertisement based on the external information and the travel information (S550), determining a reward for the advertisement based on a predetermined reward criterion and the effect (S560), and calculating a usage fee for the moving object based on the determined reward.
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公开(公告)号:US20180150428A1
公开(公告)日:2018-05-31
申请号:US15884576
申请日:2018-01-31
Applicant: Renesas Electronics Corporation
Inventor: Takahiko SUGIMOTO , Tomohiro UNE , Hiroshi UEDA , Ryoji HASHIMOTO , Toshiyuki KAYA
CPC classification number: G06F13/4221 , G06F13/00 , G06F13/4009 , G06F13/4027
Abstract: A data processing device includes a data selector circuit that divides a plurality of types of data into another plurality of types of data in accordance with a classification of the data, a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data, and a data transmission circuit that transmits the plurality of types of compressed data to a terminal.
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公开(公告)号:US20170017591A1
公开(公告)日:2017-01-19
申请号:US15144561
申请日:2016-05-02
Applicant: Renesas Electronics Corporation
Inventor: Hiroshi UEDA , Ren IMAOKA , Seiji MOCHIZUKI , Toshiyuki KAYA
IPC: G06F13/28 , H04N19/436 , H04N19/423 , H04N19/184 , H04N19/169
CPC classification number: G06F13/28 , H04N19/184 , H04N19/188 , H04N19/42 , H04N19/423 , H04N19/436
Abstract: A data processing system includes a plurality of data processing devices that perform in parallel data processing on the basis of initial setup data. The data processing devices each has a unique ID and includes a plurality of registers that store the initial setup data and a transfer circuit. The transfer circuit receives packets including a payload that is the initial setup data, shared information, a destination ID and a destination address and, when the shared information indicates that the payload is the initial setup data to be set commonly into the plurality of the data processing devices including its own data processing device, transfers the payload to the register that the destination address indicates irrespective of mismatching between the destination ID and its own ID.
Abstract translation: 数据处理系统包括基于初始设置数据执行并行数据处理的多个数据处理设备。 数据处理装置各自具有唯一的ID,并且包括存储初始建立数据的多个寄存器和传送电路。 传输电路接收包括作为初始设置数据,共享信息,目的地ID和目的地地址的有效载荷的分组,并且当共享信息指示有效负载是要被共同设置到多个数据中的初始设置数据时 包括其自己的数据处理设备的处理设备将目的地地址指示的有效载荷传送到目的地ID与其自己的ID之间的不匹配。
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公开(公告)号:US20160227236A1
公开(公告)日:2016-08-04
申请号:US14970603
申请日:2015-12-16
Applicant: Renesas Electronics Corporation
Inventor: Keisuke MATSUMOTO , Katsushige MATSUBARA , Seiji MOCHIZUKI , Toshiyuki KAYA , Hiroshi UEDA
IPC: H04N19/423 , H04N19/51 , H04N19/593 , H04N19/136 , H04N19/65 , H04N19/176 , H04N19/44 , H04N19/127
CPC classification number: H04N19/423 , H04N19/127 , H04N19/136 , H04N19/139 , H04N19/159 , H04N19/172 , H04N19/176 , H04N19/433 , H04N19/44 , H04N19/51 , H04N19/593 , H04N19/65
Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.
Abstract translation: 在图像处理装置中,运动图像解码处理部根据输入流提取要解码的目标图像的特征量,并根据特征将高速缓存填充的读取大小从外部存储器改变为高速缓冲存储器 量。 特征量表示例如一个图像(帧或场)或运动矢量变化中的宏块内比例。 当宏块内比例高时,缓存填充的读取大小减小。
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