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公开(公告)号：US07698508B2
公开(公告)日：2010-04-13
申请号：US11674960
申请日：2007-02-14
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译： 一种用于数据处理系统中缓存管理的系统和方法。 数据处理系统包括处理器和存储器层级。 存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。 响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。 如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。
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公开(公告)号：US07546417B1
公开(公告)日：2009-06-09
申请号：US12173613
申请日：2008-07-15
CPC分类号： G06F12/0864 , G06F2212/1044
摘要： A method of accessing data from a cache is disclosed. Tag bits of data among sets and ways of cache lines are divided into common subtags and remaining subtags. Similarly, an access address tag is divided into an address common subtag and address remaining tag. When the index of an access address selects a set, a match comparison of the address common subtag and the selected set common subtag is performed. Also, the address remaining tag and selected set remaining subtags are compared for matching before the selected set and associated data is supplied to the requester.
摘要翻译： 公开了一种从缓存访问数据的方法。 标记数据组中的数据位和高速缓存行的方式分为常见的子标签和剩余子标签。 类似地，访问地址标签被分成地址共享子标签和地址剩余标签。 当访问地址的索引选择一个集合时，执行地址公共子标记和所选择的公共子标记的匹配比较。 此外，在选择的集合和相关联的数据被提供给请求者之前，比较地址剩余标签和选择的集合剩余子标签以进行匹配。
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公开(公告)号：US20060155934A1
公开(公告)日：2006-07-13
申请号：US11032875
申请日：2005-01-11
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译： 一种用于数据处理系统中缓存管理的系统和方法。 数据处理系统包括处理器和存储器层级。 存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。 响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。 如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。
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24.发明授权Instruction set architecture extensions for performing power versus performance tradeoffs 失效用于执行功率与性能折衷的指令集架构扩展公开(公告)号：US08589665B2
公开(公告)日：2013-11-19
申请号：US12788940
申请日：2010-05-27
申请人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F9/00
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/3013 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3885 , G06F11/302 , G06F11/3062 , G06F11/3096
摘要： Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
摘要翻译： 提供了用于处理数据处理系统的处理器中的指令的机制。 这些机制操作以在数据处理系统的处理器中接收指令，该指令包括与指令相关联的功率/性能权衡信息。 这些机制进一步操作以基于功率/性能折衷信息来确定功率/性能折衷优先级或标准，指定功率节省或关于指令的执行是否优先的性能。 此外，机构根据功率/性能折衷优先级或基于指令的功率/性能折衷信息识别的标准处理指令。
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25.发明授权Techniques for dynamically sharing a fabric to facilitate off-chip communication for multiple on-chip units 失效用于动态共享结构以促进多个片上单元的片外通信的技术公开(公告)号：US08346988B2
公开(公告)日：2013-01-01
申请号：US12786716
申请日：2010-05-25
申请人： Jian Li , William E. Speight , Lixin Zhang
发明人： Jian Li , William E. Speight , Lixin Zhang
CPC分类号： G06F1/3203 , G06F1/3253 , G06F9/5011 , Y02D10/151 , Y02D10/22
摘要： A technique for sharing a fabric to facilitate off-chip communication for on-chip units includes dynamically assigning a first unit that implements a first communication protocol to a first portion of the fabric when private fabrics are indicated for the on-chip units. The technique also includes dynamically assigning a second unit that implements a second communication protocol to a second portion of the fabric when the private fabrics are indicated for the on-chip units. In this case, the first and second units are integrated in a same chip and the first and second protocols are different. The technique further includes dynamically assigning, based on off-chip traffic requirements of the first and second units, the first unit or the second unit to the first and second portions of the fabric when the private fabrics are not indicated for the on-chip units.
摘要翻译： 一种用于共享一个结构以促进片上单元的片外通信的技术包括：当针对片上单元指示专用结构时，动态分配实现第一通信协议的第一单元到该结构的第一部分。 该技术还包括当为片上单元指示专用结构时，动态地将实现第二通信协议的第二单元分配给该结构的第二部分。 在这种情况下，第一和第二单元集成在相同的芯片中，并且第一和第二协议是不同的。 该技术还包括：当私有结构未被指示用于片上单元时，基于第一单元或第二单元的片外流量要求将第一单元或第二单元动态地分配给该结构的第一和第二部分 。
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26.发明申请DATA PROCESSING SYSTEM, PROCESSOR AND METHOD FOR VARYING A DATA PREFETCH SIZE BASED UPON DATA USAGE 有权数据处理系统，用于根据数据使用改变数据预设尺寸的处理器和方法公开(公告)号：US20100293339A1
公开(公告)日：2010-11-18
申请号：US12024163
申请日：2008-02-01
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
摘要翻译： 一种处理器中的数据处理方法，包括维护指示对高速缓存存储器检索的预取数据的需求使用的使用历史。 基于使用历史来选择由数据预取请求预取的数据量。 将数据预取请求发送到存储器层次结构，以将所选择的数据量预取到高速缓冲存储器中。
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公开(公告)号：US20090198950A1
公开(公告)日：2009-08-06
申请号：US12024239
申请日：2008-02-01
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address.
摘要翻译： 处理器包括第一地址转换引擎，第二地址转换引擎和预取引擎。 第一地址转换引擎被配置为确定与数据预取指令相关联的指针的第一存储器地址。 预取引擎被耦合到第一翻译引擎，并被配置为在第一存储器地址处提取包含在存储器的第一数据块（例如，第一高速缓存行）中的内容。 第二地址转换引擎耦合到预取引擎，并且被配置为基于第一存储器地址处的存储器的内容来确定第二存储器地址。 预取引擎还被配置为从第二存储器地址提取包括数据的第二数据块（例如，第二高速缓存行）（例如，从存储器或另一存储器）。
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28.发明申请DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT A TOUCH OF A PARTIAL CACHE LINE OF DATA 审中-公开数据处理系统，处理器和方法，支持部分缓存行数据公开(公告)号：US20090198910A1
公开(公告)日：2009-08-06
申请号：US12024174
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831
摘要： According to method of data processing in a multiprocessor data processing system, in response to a processor touch request targeting a target granule of a cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial touch request that requests a copy of only the target granule for subsequent query access. In response to a combined response to the partial touch request indicating success, the combined response representing a system-wide response to the partial touch request, the processing unit receives the target granule of the target cache line and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the cache line.
摘要翻译： 根据多处理器数据处理系统中的数据处理方法，响应于针对包含多个粒子的数据的高速缓存行的目标颗粒的处理器触摸请求，处理单元起源于多处理器数据处理系统的互连部分触摸 请求仅请求目标颗粒的副本用于后续查询访问。 响应于指示成功的部分触摸请求的组合响应，表示对部分触摸请求的系统范围响应的组合响应，处理单元接收目标高速缓存行的目标颗粒并更新目标颗粒的一致性状态 同时保持高速缓存行的至少另一个颗粒的一致性状态。
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公开(公告)号：US07506119B2
公开(公告)日：2009-03-17
申请号：US11381563
申请日：2006-05-04
申请人： Yaoqing Gao , William E. Speight , Lixin Zhang
发明人： Yaoqing Gao , William E. Speight , Lixin Zhang
CPC分类号： G06F12/0888 , G06F12/127 , Y02D10/13
摘要： A method for compiler assisted victim cache bypassing including: identifying a cache line as a candidate for victim cache bypassing; conveying a bypassing-the-victim-cache information to a hardware; and checking a state of the cache line to determine a modified state of the cache line, wherein the cache line is identified for cache bypassing if the cache line that has no reuse within a loop or loop nest and there is no immediate loop reuse or there is a substantial across loop reuse distance so that it will be replaced from both main and victim cache before being reused.
摘要翻译： 一种用于编译器辅助的受害者缓存旁路的方法，包括：将高速缓存行标识为用于受害者缓存旁路的候选者; 向硬件传送绕过受害者缓存信息; 并且检查高速缓存行的状态以确定高速缓存行的修改状态，其中如果在循环或循环嵌套内没有重用的高速缓存行并且不存在立即循环重用或那里，则高速缓存行被识别用于高速缓存绕过 是一个实质的跨循环重用距离，因此它将被重新使用之前被替换为主缓存和受害缓存。
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公开(公告)号：US09946550B2
公开(公告)日：2018-04-17
申请号：US11856170
申请日：2007-09-17
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/30094 , G06F9/384
摘要： A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.
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