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21.发明授权Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model 失效用于指定由硬件描述语言（HDL）模型描述的数字系统的拨号组的方法，系统和程序产品公开(公告)号：US06993729B2
公开(公告)日：2006-01-31
申请号：US10425070
申请日：2003-04-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A statement in at least one hardware definition language (HDL) file specifies a plurality of design entities representing a functional portion of a digital system. The plurality of design entities have an associated plurality of configuration latches each having a plurality of different possible latch values, where different sets of latch values for the plurality of configuration latches correspond to different configurations of the functional portion of the digital system. With a statement in the at least one HDL file, a Dial group entity is associated with one of the plurality of design entities. The Dial group entity has a Dial list listing a plurality of Dial entities whose settings collectively control which set of latch values is loaded into the plurality of configuration latches. Membership in the Dial group constrains all instances of the plurality of Dial entities belonging to a particular instance of the Dial group to be set as a group.
摘要翻译： 至少一种硬件定义语言（HDL）文件中的语句指定表示数字系统的功能部分的多个设计实体。 多个设计实体具有相关联的多个配置锁存器，每个配置锁存器具有多个不同的可能的锁存值，其中用于多个配置锁存器的不同的锁存值集合对应于数字系统的功能部分的不同配置。 通过至少一个HDL文件中的语句，Dial组实体与多个设计实体之一相关联。 拨号组实体具有列出多个拨号实体的拨号列表，其多个拨号实体的设置共同控制哪个锁存值集合被加载到多个配置锁存器中。 Dial组中的成员资格限制属于Dial组的特定实例的多个Dial实体的所有实例被设置为一组。
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22.发明授权Processor system and methods of triggering a block move using a system bus write command initiated by user code 失效使用由用户代码启动的系统总线写入命令来触发块移动的处理器系统和方法公开(公告)号：US08281075B2
公开(公告)日：2012-10-02
申请号：US12423355
申请日：2009-04-14
申请人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
CPC分类号： G06F12/1458 , G06F9/30047 , G06F9/30087 , G06F12/0893
摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.
摘要翻译： 用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。 特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核中的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中） 记忆）。 从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。 然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。 在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令的从设备处理特定请求类型命令。 可信内核可能包含在管理程序或操作系统中。
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23.发明申请INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW 有权信息处理系统，具有立即调度在双存储单元缓存中的负载运算，具有单个分配到写/读数据流公开(公告)号：US20100268890A1
公开(公告)日：2010-10-21
申请号：US12424228
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0897
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译： 信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。 缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。
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24.发明授权Method for cache correction using functional tests translated to fuse repair 失效使用功能测试翻译保险丝修复的缓存校正方法公开(公告)号：US07770067B2
公开(公告)日：2010-08-03
申请号：US12325272
申请日：2008-12-01
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.
摘要翻译： 一种通过操作微处理器来执行利用高速缓冲存储器的功能测试程序来校正诸如高速缓存存储器的微处理器的存储阵列中的缺陷的方法，在功能测试程序期间收集跟踪阵列中的故障数据， 使用故障数据在高速缓冲存储器中定位缺陷，以及通过设置保险丝将该位置的访问请求重新路由到冗余阵列来修复缺陷。 故障数据可能包括错误综合征和故障地址。 功能测试过程创建随机高速缓存访问序列，其使用基于随机种子的测试模式在高速缓冲存储器中引起变化的流量负载。 功能测试程序可以在完成设置一些保险丝的微处理器的非功能性内置自检之后完成。
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25.发明申请METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE EFFICIENT STORE QUEUE USAGE 有权用于链接更多有效存储队列使用的多个小型存储队列的方法公开(公告)号：US20090198867A1
公开(公告)日：2009-08-06
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译： 数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。 存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。 存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。 响应于第一段不等于第二段，第一个条目链接到第二个条目。
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26.发明授权Method for priority scheduling and priority dispatching of store conditional operations in a store queue 有权存储条件操作在存储队列中的优先级调度和优先级调度的方法公开(公告)号：US07533227B2
公开(公告)日：2009-05-12
申请号：US12033441
申请日：2008-02-19
IPC分类号： G06F12/00
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.
摘要翻译： 一种方法，系统和处理器芯片设计，用于减少完成LARX操作和接收相关联的STCX操作之间的延迟，以完成对高速缓存行的更新。 向发行处理器的存储队列的每个条目提供附加跟踪位（优先级位）。 每当在条目中放置STCX操作时，优先级位置位。 在选择由仲裁逻辑发送的条目期间，仲裁逻辑扫描每个合格条目的优先级位的值。 具有优先级位的条目在架构规则中的选择过程中被赋予优先级。 然后在既定规则内尽可能早地选择该条目进行发送。
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27.发明授权Reducing number of rejected snoop requests by extending time to respond to snoop request 有权通过延长响应窥探请求的时间来减少被拒绝的窥探请求数公开(公告)号：US07523268B2
公开(公告)日：2009-04-21
申请号：US12114790
申请日：2008-05-04
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.
摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。 输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。 失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。 调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。 通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。
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公开(公告)号：US20080235459A1
公开(公告)日：2008-09-25
申请号：US11689990
申请日：2007-03-22
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
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29.发明授权System and method for completing updates to entire cache lines with address-only bus operations 有权使用仅地址总线操作完成对整个高速缓存行的更新的系统和方法公开(公告)号：US07360021B2
公开(公告)日：2008-04-15
申请号：US10825189
申请日：2004-04-15
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失时或在RC机器获得写入许可之前数据进入状态时，不会检索高速缓存行的数据。
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30.发明申请Method for cache correction using functional tests translated to fuse repair 失效使用功能测试翻译保险丝修复的缓存校正方法公开(公告)号：US20070101194A1
公开(公告)日：2007-05-03
申请号：US11260562
申请日：2005-10-27
申请人： Walter Lockwood , Ryan Pennington , Hugh Shen , Kenneth Wright
发明人： Walter Lockwood , Ryan Pennington , Hugh Shen , Kenneth Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.
摘要翻译： 一种通过操作微处理器来执行利用高速缓冲存储器的功能测试程序来校正诸如高速缓存存储器的微处理器的存储阵列中的缺陷的方法，在功能测试程序期间收集跟踪阵列中的故障数据， 使用故障数据在高速缓冲存储器中定位缺陷，以及通过设置保险丝将该位置的访问请求重新路由到冗余阵列来修复缺陷。 故障数据可能包括错误综合征和故障地址。 功能测试过程创建随机高速缓存访问序列，其使用基于随机种子的测试模式在高速缓冲存储器中引起变化的流量负载。 功能测试程序可以在完成设置一些保险丝的微处理器的非功能性内置自检之后完成。
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