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公开(公告)号：US5909694A
公开(公告)日：1999-06-01
申请号：US873785
申请日：1997-06-12
CPC分类号： G06F12/0864
摘要： A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A multiway cache includes a single array partitioned into a plurality of cache slots and a directory, both directory and cache slots connected to the same data bus. A first cache slot is selected and accessed; and then corresponding data is accessed from alternate slots while searching said directory, thereby reducing the latency penalty for cache access.
摘要翻译： 缓存系统提供访问集合关联缓存，而不增加关键路径延迟，以减少高速缓存访问的延迟损失，减少侦听占线时间，以及响应MRU未命中和高速缓存未命中。 多路缓存包括分割成多个高速缓存时隙的单个阵列和连接到同一数据总线的目录和高速缓冲存储器的目录。 选择并访问第一个高速缓存槽; 然后在搜索所述目录时从备用时隙访问对应的数据，从而减少高速缓存访问的等待时间。
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2.发明申请METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE EFFICIENT STORE QUEUE USAGE 有权用于链接更多有效存储队列使用的多个小型存储队列的方法公开(公告)号：US20090198867A1
公开(公告)日：2009-08-06
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译： 数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。 存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。 存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。 响应于第一段不等于第二段，第一个条目链接到第二个条目。
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3.发明授权Branch target cache and method for efficiently obtaining target path instructions for tight program loops 失效分支目标缓存和方法，用于有效地获取严格程序循环的目标路径指令公开(公告)号：US06829702B1
公开(公告)日：2004-12-07
申请号：US09626247
申请日：2000-07-26
IPC分类号： G06F932
CPC分类号： G06F9/381 , G06F9/3017 , G06F9/3804 , G06F9/3806 , G06F9/3885
摘要： A processor that efficiently obtains target path instructions in the presence of tight program loops includes at least one execution unit for executing instructions and instruction sequencing logic that supplies instructions to the at least one execution unit for execution. The instruction sequencing logic includes an instruction fetch buffer and a branch prediction unit including a branch target cache. In response to prediction of a branch instruction as taken, the branch target cache causes multiple copies of a target instruction group to be loaded into the instruction fetch buffer under the assumption that the branch instruction is a member of the target instruction group. Thereafter, the branch target cache causes all but one of the multiple copies to be canceled from the instruction fetch buffer prior to dispatch if the branch instruction does not belong to the target instruction group. Thus, the branch target cache can meet the instruction fetch cycle time of the processor even for the worst case condition in which the branch instruction is within the target instruction group.
摘要翻译： 在存在紧密程序循环的情况下有效地获得目标路径指令的处理器包括至少一个执行单元，用于执行向至少一个执行单元提供指令以执行的指令和指令排序逻辑。 指令排序逻辑包括指令获取缓冲器和包括分支目标高速缓存的分支预测单元。 响应于如所采用的分支指令的预测，在假设分支指令是目标指令组的成员的假设下，分支目标高速缓存使目标指令组的多个副本被加载到指令获取缓冲器中。 此后，如果分支指令不属于目标指令组，则分支目标高速缓存使得在分派之前从指令获取缓冲器中取消多个副本中的一个副本。 因此，即使在分支指令在目标指令组内的最坏情况条件下，分支目标高速缓存也可以满足处理器的指令获取周期时间。
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4.发明授权Oversized data detection hardware for data processors which store data at variable length destinations 失效用于在可变长度目的地存储数据的数据处理器的超大数据检测硬件
公开(公告)号：US4021655A
公开(公告)日：1977-05-03
申请号：US671857
申请日：1976-03-30
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3016
摘要： Size exception detection hardware for use with a digital data processor arithmetic unit for providing high-speed detection of lost data which results from storing an arithmetic result in a destination which is smaller than one or both of the source operands. In response to data processing machine instructions, the arithmetic unit performs arithmetic operations on variable length operands and sends the arithmetic results to variable length destinations. The operand and destination lengths are specified by length fields in the machine instruction. The destination length is specified independently of at least one of the operand lengths and hence may be less than such operand length. The size exception detection hardware looks at both the output field of the arithmetic unit and the destination length field in the machine instruction and generates a size exception program interrupt signal when the part of the arithmetic unit output field located outside of the destination length contains significant data. The size exception interrupt is generated during the same machine control cycle during which the arithmetic unit performs the arithmetic operation which gives rise to the size exception.
摘要翻译： 用于与数字数据处理器运算单元一起使用的大小异常检测硬件，用于提供由算术结果存储在小于一个或两个源操作数的目的地而导致的丢失数据的高速检测。 响应于数据处理机器指令，算术单元对可变长度操作数执行算术运算，并将算术结果发送到可变长度目的地。 操作数和目标长度由机器指令中的长度字段指定。 目标长度与操作数长度中的至少一个无关地指定，因此可以小于该操作数长度。 尺寸异常检测硬件在运算单元的输出域和机器指令中的目的地长度字段两者之间，当位于目的地长度之外的运算单元输出字段的部分包含有效数据时，生成大小异常程序中断信号 。 在相同的机器控制周期期间产生尺寸异常中断，在此期间，运算单元执行引起尺寸异常的算术运算。
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5.发明授权Chaining multiple smaller store queue entries for more efficient store queue usage 有权链接多个较小的存储队列条目，以实现更高效的存储队列使用公开(公告)号：US08166246B2
公开(公告)日：2012-04-24
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译： 数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。 存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。 存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。 响应于第一段不等于第二段，第一个条目链接到第二个条目。
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公开(公告)号：US5940877A
公开(公告)日：1999-08-17
申请号：US873783
申请日：1997-06-12
CPC分类号： G06F12/0864 , G06F12/1054 , G06F2212/6082
摘要： A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. The cache array is accessed by multiplexing two most-recently-used (MRU) arrays which are addressed and accessed substantially in parallel with effective address generation, the outputs of which MRU arrays are generated, one by assuming a carryin of zero, and the other by assuming a carryin of one to the least significant bit of the portion of the effective addressed used to access the MRU arrays. The hit rate in the MRU array is improved by hashing within an adder the adder's input operands with predetermined additional operand bits.
摘要翻译： 缓存系统提供访问集合关联缓存，而不增加关键路径延迟，以减少高速缓存访问的延迟损失，减少侦听占线时间，以及响应MRU未命中和高速缓存未命中。 通过复用两个最近使用的（MRU）阵列来访问高速缓存阵列，其基本上与生成有效地址的MRU阵列的输出相平行地寻址和访问，其中一个通过假定为零，另一个 通过假设一个进位到用于访问MRU阵列的有效寻址部分的最低有效位。 MRU阵列中的命中率通过加法器中的加法器的加法器的输入操作数与预定的附加操作数位进行散列得到改善。
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公开(公告)号：US5701430A
公开(公告)日：1997-12-23
申请号：US483419
申请日：1995-06-07
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3816 , G06F9/3842 , G06F9/3853
摘要： A certain class of computer has been previously described which has improved performance through the analysis of instructions comprising the computer's control program and appending control information to the instructions in the form of tags. One such computer analyzes instruction cache lines as they are loaded into the cache to create the tags. A disadvantage of that design is the inability to create control information for portions of the cache line whose control tags depend on instructions in another cache line as well as the line being loaded. A method and apparatus is described herein which facilitates creation of control tags based on instructions which reside in different cache lines. The method permits a more complete analysis to be performed, thereby improving processor performance.
摘要翻译： 以前已经描述了某种类型的计算机，其通过分析包括计算机的控制程序的指令并且以标签的形式将控制信息附加到指令来提高性能。 一个这样的计算机分析指令高速缓存行，因为它们被加载到高速缓存中以创建标签。 该设计的缺点是无法为其控制标签依赖于另一高速缓存行中的指令以及被加载的行的高速缓存行的部分创建控制信息。 本文描述了一种方法和装置，其有助于基于驻留在不同高速缓存行中的指令来创建控制标签。 该方法允许执行更完整的分析，从而提高处理器性能。
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