公开(公告)号：US07772887B2

公开(公告)日：2010-08-10

申请号：US12181621

申请日：2008-07-29

申请人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03K19/0175 ,  G06F13/36

CPC分类号： G06F13/4072 ,  G06F13/385

摘要： A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.

摘要翻译： 信号接口电路具有用于将主机电路通信耦合到多个外围设备的外围电路的信号路径。 信号路径中的通信信号为周边信号电平。 信号路径具有适于在主机电路和外围电路之间传送信号的电子部件。 信号路径中的电子元件具有小于外围信号电平的可靠性限制。 信号路径中的电子部件的配置允许以外围信号电平进行信号的通信。

公开(公告)号：US20100030924A1

公开(公告)日：2010-02-04

申请号：US12181621

申请日：2008-07-29

申请人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： G06F3/00

CPC分类号： G06F13/4072 ,  G06F13/385

摘要： A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.

摘要翻译： 信号接口电路具有用于将主机电路通信耦合到多个外围设备的外围电路的信号路径。 信号路径中的通信信号为周边信号电平。 信号路径具有适于在主机电路和外围电路之间传送信号的电子部件。 信号路径中的电子元件具有小于外围信号电平的可靠性限制。 信号路径中的电子部件的配置允许以外围信号电平进行信号的通信。

公开(公告)号：US20100026364A1

公开(公告)日：2010-02-04

申请号：US12181672

申请日：2008-07-29

申请人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03L5/00

CPC分类号： H03K19/00315 ,  H03K19/018507 ,  H03K19/018585

摘要： An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level.

摘要翻译： 接口输入具有适于接收高于主机电路的电子部件可以可靠地处理的最大信号电平的输入信号电平的输入电路。 输入电路将输入信号的电平移动到期望的信号电平。 保持器电路耦合到输入电路，并保持与输入信号电平一致的移位信号的触发电平。

公开(公告)号：US20100026348A1

公开(公告)日：2010-02-04

申请号：US12181655

申请日：2008-07-29

申请人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03K3/00 ,  H03L5/00

CPC分类号： H03K19/00315 ,  H03K19/017581 ,  H03K19/018507

摘要： A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.

摘要翻译： 用于接口电路的信号驱动器具有第一级电平移位器，以接收输入信号并以第一信号电平输出信号。 信号驱动器还具有耦合到第一级电平移位器的第二级电平移位器，以在第二信号电平输出信号。 第一级和第二级电平移位器的电子部件具有小于第二信号电平的可靠性限制。 第一级电平移位器和第二级电平转换器的第一和第二级配置防止当处理用于在第二信号电平输出的信号时将电子部件暴露于高于可靠性限制的端对端信号电平。

公开(公告)号：US20090033400A1

公开(公告)日：2009-02-05

申请号：US11832128

申请日：2007-08-01

申请人： Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03L5/00

CPC分类号： H03K19/018592 ,  H03K19/00384

摘要： Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.

摘要翻译： 提出了用于耐压漂浮N阱电路的方法和装置。 提供了一种用于减轻由输入电压引起的漏电流的装置，其包括具有耦合到正电压源的源极和耦合到浮动节点的漏极的第一晶体管。 该装置还可以包括耦合到负电压源和第一晶体管的可控下拉通路，其中可控下拉通道被配置为在第一状态期间导通第一晶体管并上拉浮动节点。 该装置还可以包括具有耦合到第一晶体管的栅极的源极和耦合到浮动节点的漏极的第二晶体管，其中第二晶体管被配置为在第二状态期间将浮动节点置于浮动电位。

公开(公告)号：US20090021405A1

公开(公告)日：2009-01-22

申请号：US12105152

申请日：2008-04-17

申请人： Vivek Mohan ,  Abhay Dixit

发明人： Vivek Mohan ,  Abhay Dixit

IPC分类号： H03K5/08 ,  H03M9/00

CPC分类号： H04L25/0292 ,  H03K19/017 ,  H04L25/0272

摘要： An electronic device is described. The electronic device includes a first integrated circuit (IC) and a second integrated circuit (IC). The electronic device also includes a multiplexer configured to multiplex a parallel data signal into a serial data signal, and a transmitter configured to transmit the serial data signal from the first IC to the second IC. The electronic device further includes a receiver configured to receive the serial data signal. The receiver includes a clamp circuit configured to clamp the voltage swing of an analog node within a determined range. The clamp also helps to extend the bandwidth of the receiver.

摘要翻译： 描述电子设备。 电子设备包括第一集成电路（IC）和第二集成电路（IC）。 电子设备还包括被配置为将并行数据信号复用为串行数据信号的多路复用器，以及被配置为将串行数据信号从第一IC传输到第二IC的发射器。 电子设备还包括被配置为接收串行数据信号的接收器。 接收机包括钳位电路，其被配置为将模拟节点的电压摆幅钳位在确定的范围内。 钳位还有助于扩展接收机的带宽。

公开(公告)号：US07471110B2

公开(公告)日：2008-12-30

申请号：US11389332

申请日：2006-03-23

申请人： Abhay Dixit ,  Mehdi Hamidi Sani ,  Vivek Mohan

发明人： Abhay Dixit ,  Mehdi Hamidi Sani ,  Vivek Mohan

IPC分类号： H03K19/094

CPC分类号： H03K19/018514 ,  H01L2224/49175 ,  H01L2924/3011 ,  H01L2924/30111 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/0282 ,  H04L25/0294 ,  H01L2924/00

摘要： A transceiver interface for data transfer between two integrated circuits (ICs or “chips”) utilizes a current mode technique rather than conventional voltage mode differential signaling techniques. A current pulse is injected into one of two transmission wires based on a signal value to be transmitted (e.g., logic “0” or “1”) by a driver on a transmitting chip. The current pulse is received as a differential current signal at a receive block in a receiving chip. The differential signal is converted to a low swing differential voltage signal by current comparators. The differential voltage signal may be detected by an op-amp receiver which outputs the appropriate signal value.

摘要翻译： 用于两个集成电路（IC或“芯片”）之间的数据传输的收发器接口利用电流模式技术而不是传统的电压模式差分信令技术。 基于传输芯片上的驱动器将要发送的信号值（例如，逻辑“0”或“1”），将电流脉冲注入到两条传输线之一中。 在接收芯片中的接收块处接收当前脉冲作为差分电流信号。 差分信号由电流比较器转换为低摆幅差分电压信号。 差分电压信号可以由输出适当信号值的运算放大器接收器检测。

公开(公告)号：US20050231260A1

公开(公告)日：2005-10-20

申请号：US10825481

申请日：2004-04-14

申请人： Vaishnav Srinivas ,  Vivek Mohan

发明人： Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03K3/356 ,  H03K17/0812 ,  H03K19/00 ,  H03B1/00

CPC分类号： H03K19/0013 ,  H03K3/356113 ,  H03K17/08122

摘要： A break-before-make predriver for disabling a PFET of an output driver before enabling an NFET, and vice versa. The predriver includes an input inverter, two cross-coupled inverters, and output buffers. The predriver provides enhanced break-before-make action through sizing the NFETs larger than the PFETs in the predriver's cross-coupled inverters. The input inverter, the cross-coupled inverters and the first and second output buffers are sized with respect to each other such that substantially equal break before make action is provided on both rising and falling edges. The predriver also includes level-shifting capabilities through a different voltage supply at the PFETs of the cross-coupled inverter. The predriver also includes two data output nodes for connection to the two inputs of an output driver. The predriver provides for tristate action by disabling the signal from the predriver output nodes.

摘要翻译： 用于在启用NFET之前禁用输出驱动器的PFET的前置制造预驱动器，反之亦然。 预驱动器包括输入反相器，两个交叉耦合的反相器和输出缓冲器。 预驱动器通过将大于预驱动器交叉耦合逆变器中的PFET的NFET尺寸调整，从而提供增强的“先行后制”动作。 输入反相器，交叉耦合反相器和第一和第二输出缓冲器相对于彼此大小，使得在上升沿和下降沿两者之间提供在作用之前基本相等的断开。 预驱动器还包括通过交叉耦合逆变器的PFET处的不同电压源的电平转换能力。 预驱动器还包括用于连接到输出驱动器的两个输入的两个数据输出节点。 预驱动器通过禁用来自预驱动输出节点的信号来提供三态动作。

公开(公告)号：US08605604B1

公开(公告)日：2013-12-10

申请号：US12971667

申请日：2010-12-17

申请人： Vivek Mohan ,  Hsui-Ping Peng

发明人： Vivek Mohan ,  Hsui-Ping Peng

IPC分类号： H04L12/26

CPC分类号： H04L41/145 ,  H04L43/10

摘要： Apparatus having corresponding methods and non-transitory computer-readable media comprise: a wireless local-area network (WLAN) module comprising a receiver configured to receive a WLAN signal into the WLAN module; a transmitter; and a loopback controller configured to selectively loop back the WLAN signal to the transmitter, wherein the transmitter is configured to transmit the looped-back WLAN signal from the WLAN module.

摘要翻译： 具有相应方法和非暂时性计算机可读介质的装置包括：无线局域网（WLAN）模块，包括被配置为将WLAN信号接收到所述WLAN模块中的接收机; 发射机 以及环回控制器，被配置为选择性地将所述WLAN信号环回到所述发射机，其中所述发射机被配置为从所述WLAN模块发射所述环回WLAN信号。

公开(公告)号：US08593203B2

公开(公告)日：2013-11-26

申请号：US12181672

申请日：2008-07-29

申请人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03L5/00

CPC分类号： H03K19/00315 ,  H03K19/018507 ,  H03K19/018585

摘要： An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level.

摘要翻译： 接口输入具有适于接收高于主机电路的电子部件可以可靠地处理的最大信号电平的输入信号电平的输入电路。 输入电路将输入信号的电平移动到期望的信号电平。 保持器电路耦合到输入电路，并保持与输入信号电平一致的移位信号的触发电平。