公开(公告)号：US06570885B1

公开(公告)日：2003-05-27

申请号：US09439011

申请日：1999-11-12

申请人： Thomas Anthony Gregg

发明人： Thomas Anthony Gregg

IPC分类号： H04L1254

CPC分类号： H04L47/6225 ,  G06F12/0813 ,  H04L47/10 ,  H04L47/19 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L49/9089

摘要： Defines and handles segments in messages to place pauses and interruptions within the communication of a message between transmitted segments of the message. A port cache of the destination node of each transmitted message obtains a message control block (MCB) which is used to control the reception of inbound segments within each message sent or received by the node. Each MCB stays in the cache only while its message is being communicated to the port and may be castout between segments in its message when there is no empty cache entry to receive a MCB for a current message being communicated but not having its MCB in the cache. Different types of dynamic priorities are written in status fields in each non-empty cache entry to enable a current cache entry to be castout when it is most likely to have the longest wait for being needed next in the cache for a segment communication to its message, which reduces cache castout thrashing to increase the average reception speed for communicating messages in the network. If a common link switch is used in a network to connect links to all nodes, the segment structures in each message is musts be preserved when packets of each message are passed through the switch to a destination node which uses the castout controlled communication cache taught herein.

摘要翻译： 定义和处理消息中的段，以在消息的传输段之间的消息通信中暂停和中断。 每个发送消息的目的地节点的端口高速缓存获得消息控制块（MCB），该消息控制块用于控制由节点发送或接收的每个消息内的入站段的接收。 每个MCB只有当其消息被传送到端口时才停留在缓存中，并且当没有空缓存条目来接收正在通信的当前消息的MCB但在高速缓存中没有其MCB时，可以在其消息中的段之间进行舍弃 。 不同类型的动态优先级被写入每个非空高速缓存条目中的状态字段中，以使当前缓存条目最有可能在高速缓存中需要等待下一次等待其消息的段通信时被抛出 ，这减少了高速缓存丢弃的抖动，以增加在网络中传达消息的平均接收速度。 如果在网络中使用公共链路交换机将链路连接到所有节点，则每个消息的分组必须被保留，每个消息的分组通过交换机传递到目的地节点，该目的节点使用本文中教导的控制通信缓存 。

公开(公告)号：US5948060A

公开(公告)日：1999-09-07

申请号：US788755

申请日：1997-01-24

申请人： Thomas Anthony Gregg ,  Kulwant Mundra Pandey

发明人： Thomas Anthony Gregg ,  Kulwant Mundra Pandey

IPC分类号： G06F15/16 ,  G06F15/163 ,  H04L12/56 ,  G06F13/00

CPC分类号： H04L49/9047 ,  H04L49/90 ,  H04L49/901

摘要： Speeds up a commanded system to read or write data for a large number of data frames transmitted on a link by executing a TRANSFER STRUCTURE instruction that automatically controls the reading or writing of a large number of scattered storage blocks in the storage of the commanded system containing, or to contain, the data transmitted on the link.

摘要翻译： 通过执行TRANSFER STRUCTURE指令来读取或写入大量数据帧的数据，加速指令系统读取或写入数据，该指令自动控制指令系统的存储中大量分散存储块的读取或写入， ，或包含在链路上发送的数据。

公开(公告)号：US5944797A

公开(公告)日：1999-08-31

申请号：US864583

申请日：1997-05-28

申请人： Thomas Anthony Gregg ,  Kulwant Mundra Pandey

发明人： Thomas Anthony Gregg ,  Kulwant Mundra Pandey

IPC分类号： G06F13/12 ,  H04L12/56 ,  H04L29/08 ,  G06F13/00

CPC分类号： G06F13/126 ,  H04L49/90

摘要： The present invention significantly reduces or eliminates the involvment of central processors in the message block handling of received communication-link responses within a Central Processing Complex (CPC). When a commanding system sends a command, it must receive a response frame from the commanded system indicating if the command was correctly received or not. A significant amount of time is required for the commanding system processor to move the received response frame from a receiving link buffer to an area in the CPC memory. The preferred embodiment avoids the need for having a commanding system processor either wait for or be interrupted to handle the response frame. The preferred embodiment provides advanced preparation of a data mover in a manner to enable the data mover in the computer system to handle the reception of each response frame without involving the commanding system processor. The commanding system is signalled by the data mover on the completion of the response handling to make the completion of each command known to the program which issued the command.

摘要翻译： 本发明显着地减少或消除了在中央处理复合体（CPC）内的接收的通信链路响应的消息块处理中的中央处理器的引入。 当命令系统发送命令时，它必须从命令系统接收到响应帧，指示该命令是否被正确接收。 命令系统处理器需要大量时间将接收的响应帧从接收链路缓冲区移动到CPC存储器中的一个区域。 优选实施例避免了使命令系统处理器等待或被中断以处理响应帧的需要。 优选实施例以使得计算机系统中的数据移动器能够处理每个响应帧的接收而不涉及命令系统处理器的方式提供数据移动器的高级准备。 在完成响应处理后，由数据移动设备发出命令系统，以完成发出命令的程序所知道的每个命令。

公开(公告)号：US5938786A

公开(公告)日：1999-08-17

申请号：US565598

申请日：1995-11-30

申请人： Thomas Anthony Gregg

发明人： Thomas Anthony Gregg

IPC分类号： H04L1/18 ,  G08C25/02

CPC分类号： H04L1/1835 ,  H04L1/1851 ,  H04L1/1874 ,  H04L1/1883

摘要： An apparatus and method is provided for asynchronously transmitting data across fiber optical cables in a serial manner. Frames are provided as a mechanism to transmit associated data over a serial link and to tie the data being transmitted to a particular buffer set. Each outstanding request for each buffer set is individually timed to detect lost frames, and each buffer set maintains a state that keeps track of the progress and sequence of received frames. When transmission errors occur in the frames, the errors may affect only the information field in which case there is enough information in the header to identify the frame. If a frame is damaged, any outstanding operations for the affected buffer set are cleared, and any commands are brought to a logical ending point. The computer system which originates the frames is then notified of the specific nature of the error, and which information is supplied to help the originating computer system efficiently conclude the recovery procedure.

摘要翻译： 提供一种用于以串行方式跨光纤光缆异步传输数据的装置和方法。 提供帧作为通过串行链路传输关联数据并将正被发送的数据与特定缓冲器组合的机制。 每个缓冲器组的每个未完成的请求被单独定时以检测丢失的帧，并且每个缓冲器组保持跟踪接收帧的进度和顺序的状态。 当帧中出现传输错误时，错误可能仅影响信息字段，在这种情况下，报头中有足够的信息来识别帧。 如果帧损坏，则清除受影响的缓冲区的任何未完成的操作，并将任何命令带到逻辑终点。 然后，发送帧的计算机系统通知错误的特定性质，并且提供哪些信息以帮助始发计算机系统有效地完成恢复过程。

公开(公告)号：US07099955B1

公开(公告)日：2006-08-29

申请号：US09692351

申请日：2000-10-19

申请人： Thomas Anthony Gregg ,  Gregory Francis Pfister ,  Renato John Recio ,  Steven Mark Thurber

发明人： Thomas Anthony Gregg ,  Gregory Francis Pfister ,  Renato John Recio ,  Steven Mark Thurber

IPC分类号： G06F15/173

CPC分类号： H04L29/12254 ,  H04L29/12783 ,  H04L61/2038 ,  H04L61/35 ,  H04L67/1097 ,  Y10S707/99932

摘要： A method for routing System Area Network (SAN) packets to multiple partitions within a single end node is provided. A range of Local Identification addresses (LIDs) are assigned to a channel adapter port within the SAN. Lower order bits within the LID are then assigned to select the particular partition in the end node. The Local ID Mask Control (LMC) field is used to assign multiple LIDs to a single port, using those low order bits to then route the message to the appropriate partition in the end node.

摘要翻译： 提供了将系统区域网（SAN）数据包路由到单个端节点内的多个分区的方法。 本地标识地址（LID）的范围被分配给SAN中的通道适配器端口。 然后分配LID中的低位位以选择端节点中的特定分区。 本地ID掩码控制（LMC）字段用于将多个LID分配给单个端口，使用这些低位位置将消息路由到最终节点中的相应分区。

公开(公告)号：US06665809B1

公开(公告)日：2003-12-16

申请号：US09573015

申请日：2000-05-17

申请人： Gottfried Andreas Goldrian ,  Thomas Anthony Gregg

发明人： Gottfried Andreas Goldrian ,  Thomas Anthony Gregg

IPC分类号： G06F104

CPC分类号： G04G7/00 ,  G06F1/14 ,  H04J3/0697

摘要： The basic idea comprised of the present invention is to decentralize the generation of time information without suffering from the cost disadvantages expectable due to use of prior art techniques necessary for synchronizing and correcting a plurality instead of only one or two of time suppliers caused by said decentralization. This is achieved by the approach not to readjust the oscillator(s), but, instead, to accept the inaccuracy of the physical device ‘oscillator’ but to measure its inaccuracy and to correct it with the aid of a continuos correction calculation which is advantageously done in a digital way under usage of ETS input information and system oscillator output information.

摘要翻译： 由本发明构成的基本思想是分散时间信息的产生，而不会因为使用现有技术技术所需的成本缺点而不会因同步和纠正多个而不是由所述分散产生的时间供应商中的一个或两个 。 这是通过不重新调整振荡器的方法实现的，而是接受物理设备的振荡器的不准确性，而是借助于有利的连续校正计算来测量其不准确性并进行校正 在使用ETS输入信息和系统振荡器输出信息的情况下以数字方式完成。

公开(公告)号：US5706432A

公开(公告)日：1998-01-06

申请号：US474574

申请日：1995-06-07

申请人： David Arlen Elko ,  Gottfried Andreas Goldrian ,  Steven Neil Goss ,  Thomas Anthony Gregg ,  Audrey Ann Helffrich ,  Joseph Arthur Williams

发明人： David Arlen Elko ,  Gottfried Andreas Goldrian ,  Steven Neil Goss ,  Thomas Anthony Gregg ,  Audrey Ann Helffrich ,  Joseph Arthur Williams

IPC分类号： G06F13/12 ,  G06F15/17 ,  G06F15/167

CPC分类号： G06F13/126 ,  G06F15/17

摘要： Computer system processing complexes which can operate actually or apparently synchronously and in parallel or asynchronously in a network have a coupling facility for sending and receiving commands, responses, and data. The memory for the central processing complexes (which is accessible to each of the processing elements) is provided with storage for messages and data for coupling over a communication channel interface. Each of a plurality of processing elements (CPC) has data objects used to maintain state information for shared data in the coupling facility storage. The coupling facility can receive both message commands and data, sending data and responses to messages, and sending and receiving secondary messages. The processing element accessible memory provides a state information buffer control information operation memory block for describing the hardware communication environment associated with the computer system mechanism for storage of state information pertaining to a communications buffer residing in said coupling facility storage. The communication channel has a set of address registers. The system employs four new instructions, PREPARE CHANNEL BUFFER, SIGNAL CHANNEL BUFFER, MOVE CHANNEL BUFFER DATA, and TEST CHANNEL BUFFER, to enable a coupling facility control program to directly manipulate the address registers and control the flow of data, commands and responses between the coupling-facility storage and communication channels for the central processing elements. This provides a direct interface between the coupling facility and an intersystem communication channel for the receipt of messages and data and the related receiving functions.

摘要翻译： 可以在网络中实际或明显同步并行或异步操作的计算机系统处理复合体具有用于发送和接收命令，响应和数据的耦合设备。 用于中央处理复合体（每个处理元件可访问）的存储器提供有用于通过通信信道接口耦合的消息和数据的存储。 多个处理元件（CPC）中的每一个具有用于维持耦合设备存储器中共享数据的状态信息的数据对象。 耦合设施可以接收消息命令和数据，发送数据和对消息的响应，以及发送和接收辅助消息。 处理元件可访问存储器提供状态信息缓冲器控制信息操作存储器块，用于描述与计算机系统机构相关联的硬件通信环境，用于存储与驻留在所述耦合设备存储器中的通信缓冲器有关的状态信息。 通信通道具有一组地址寄存器。 该系统采用四个新的指令：PREPARE CHANNEL BUFFER，SIGNAL CHANNEL BUFFER，MOVE CHANNEL BUFFER DATA，以及TEST CHANNEL BUFFER，以实现一个耦合设备控制程序，直接操纵地址寄存器，并控制数据流，命令和响应 耦合设备存储和通信信道用于中央处理元件。 这提供了耦合设施和用于接收消息和数据以及相关接收功能的系统间通信信道之间的直接接口。

公开(公告)号：US5651033A

公开(公告)日：1997-07-22

申请号：US480705

申请日：1995-06-07

申请人： Thomas Anthony Gregg ,  Robert Stanley Capowski ,  Daniel Francis Casper ,  Frank David Ferraiolo

发明人： Thomas Anthony Gregg ,  Robert Stanley Capowski ,  Daniel Francis Casper ,  Frank David Ferraiolo

IPC分类号： G06F13/42 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04 ,  H04L12/56 ,  H04L25/14 ,  H04L25/49 ,  H04L29/06

CPC分类号： H04L29/06 ,  G06F13/4278 ,  H04L25/14 ,  H04L25/4908 ,  H04L7/041 ,  H04L2007/045 ,  H04L69/14 ,  H04L7/0008

摘要： A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a run-length-limited code, along with its idle and data character sequences. Each of the plurality of bytes is transmitted on a separate conducting line along with a transmit clock signal that is also transmitted on a separate line. At the receiver, the data stream on each line is separately phase aligned with the clock, and bit aligned.

摘要翻译： 自定义接口（STI）链接两个物理上分离的系统或节点。 发送状态机将串行比特流中的每个单词形成多个字节，并生成空闲和数据字符序列。 每个字节分别以游程长度限制的代码及其空闲和数据字符序列编码。 多个字节中的每一个与分离的线路上发送的发送时钟信号一起在单独的导线上发送。 在接收机上，每行上的数据流与时钟分开相位对齐，并且位对齐。

公开(公告)号：US06188675B1

公开(公告)日：2001-02-13

申请号：US08702778

申请日：1996-08-23

申请人： Daniel Francis Casper ,  Thomas Anthony Gregg ,  George Wayne Nation ,  Kenneth Blair Ocheltree ,  Charles Bertram Perkins, Jr.

发明人： Daniel Francis Casper ,  Thomas Anthony Gregg ,  George Wayne Nation ,  Kenneth Blair Ocheltree ,  Charles Bertram Perkins, Jr.

IPC分类号： H04L1228

CPC分类号： H04L45/02 ,  H04L45/26

摘要： A system and method for progressively identifying and configuring the nodes of a network having an unknown or partially unknown topology are presented. A special all-node address indicator is designated for insertion in a packet to be sent from a given node with known node address to a next adjacent node with unknown node address. Each node contains a port control register for each port of the node which when set instructs the node to insert the all-node address indicator into a packet to be forwarded to a next adjacent node in the network with unknown node address. The port control registers are remotely selectively set by one or more managing nodes of the network. Race condition is avoided by provision of a set count register associated with an address node register and managing node address register within each node of the network. A node can be configured only if the previously read set count value remains unchanged between reading of and writing to the address node register or managing node address register. Provision for identifying additions, deletions and other changes to the network automatically is also provided.

摘要翻译： 提出了用于逐渐识别和配置具有未知或部分未知拓扑的网络的节点的系统和方法。 指定特殊的全节点地址指示符用于插入到具有已知节点地址的给定节点发送到具有未知节点地址的下一个相邻节点的分组中。 每个节点包含一个端口控制寄存器，用于节点的每个端口，当设置时指示节点将全节点地址指示符插入到要转发到具有未知节点地址的网络中的下一个相邻节点的数据包中。 端口控制寄存器由网络的一个或多个管理节点进行远程选择性设置。 通过提供与地址节点寄存器相关联的设置计数寄存器和管理网络的每个节点内的节点地址寄存器来避免竞争条件。 只有在先前读取的设置计数值在读取和写入地址节点寄存器或管理节点地址寄存器之间保持不变时才能配置节点。 还提供了自动识别网络添加，删除和其他更改的规定。

公开(公告)号：US5680575A

公开(公告)日：1997-10-21

申请号：US443293

申请日：1995-05-17

申请人： Neil George Bartow ,  Robert Stanley Capowski ,  Louis Thomas Fasano ,  Thomas Anthony Gregg ,  Gregory Salyer ,  Douglas Wayne Westcott

发明人： Neil George Bartow ,  Robert Stanley Capowski ,  Louis Thomas Fasano ,  Thomas Anthony Gregg ,  Gregory Salyer ,  Douglas Wayne Westcott

IPC分类号： G06F13/12 ,  G06F15/17 ,  G06F15/173 ,  H04J3/06 ,  H04L7/10 ,  H04L29/06 ,  H04L29/08 ,  H04L29/14 ,  G06F13/14

CPC分类号： G06F13/122 ,  G06F15/17 ,  G06F15/17343 ,  H04J3/0629 ,  H04L29/06 ,  H04L69/40 ,  H04L7/10 ,  H04L69/14 ,  H04L69/323 ,  H04L69/324

摘要： A system for resetting a cache in a first device connected by a multilinelink to a memory in a second device. A transceiver in the first element connects to one end of each of the link lines and a transceiver in the second device connects to the other end. The transmitter in the first device transceiver is disabled in response to a failure of the transceiver to receive messages from the second device. The transmitter in the first device transceiver also selectively sends a reset sequence to the receiver in the second device. A detector detects when all of the receivers in the second device have either received a reset sequence or have detected that a transmitter in the first device is disabled. The detector sets a latch in response, representing that data in the second device cache is invalid. Optionally, the second device has responders which send responses over the link lines indicating receipt of a reset sequence. The transmitters in the first device switch to a disabled state when the responses are not received within a specified period.

摘要翻译： 一种用于将通过多连接器连接的第一设备中的高速缓存重置到第二设备中的存储器的系统。 第一元件中的收发器连接到每个链路线的一端，并且第二设备中的收发器连接到另一端。 第一设备收发器中的发射机响应于收发器从第二设备接收消息的故障被禁用。 第一设备收发器中的发射机还选择性地向第二设备中的接收机发送复位序列。 检测器检测到第二设备中的所有接收器何时已经接收到重置序列或检测到第一设备中的发射机被禁用。 检测器设置响应的锁存器，表示第二设备高速缓存中的数据无效。 可选地，第二设备具有通过链路线发送响应的响应器，指示接收到重置序列。 当在指定时间内没有收到响应时，第一个设备中的发射机切换到禁用状态。