公开(公告)号：US07451294B2

公开(公告)日：2008-11-11

申请号：US10631629

申请日：2003-07-30

申请人： Zeev Sperber ,  Yuval Bustan ,  Robert Valentine

发明人： Zeev Sperber ,  Yuval Bustan ,  Robert Valentine

IPC分类号： G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single instruction multiple data extension type operands. Once received, the macro-instruction is decoded into a first micro-operation (uOP) and a second uOP. Once decoded, a signal is asserted to disable source operand override logic if the first micro-operation updates a logical destination register that matches a logical source register of the micro-operation. Otherwise, the mutual source override is active and executed by a register alias table (RAT) when uOP with matching logic source and destination register are detected in a same clock cycle. In doing so, macro-instructions having 128-bit operands may be processed using, for example, two uOPs (one for the lower half and one for the upper half) in a 64-bit implementation, while preserving the atomicity of the original instruction.

摘要翻译： 一种使用源超控的两个微操作流的方法和装置。 在一个实施例中，该方法包括识别具有一个或多个流单个指令多个数据扩展类型操作数的宏指令。 一旦接收到，宏指令被解码成第一微操作（uop）和第二uop。 一旦被解码，如果第一微操作更新与微操作的逻辑源寄存器匹配的逻辑目标寄存器，则信号被断言以禁用源操作数覆盖逻辑。 否则，当在相同的时钟周期中检测到具有匹配逻辑源和目标寄存器的UOP时，互源替代是激活的并由寄存器别名表（RAT）执行。 这样，具有128位操作数的宏指令可以在64位实现中使用例如两个uOP（一个用于下半部分，一个用于上半部分）来处理，同时保持原始指令的原子性 。

公开(公告)号：US07206921B2

公开(公告)日：2007-04-17

申请号：US10407468

申请日：2003-04-07

申请人： Zeev Sperber ,  Robert Valentine ,  Simcha Gochman

发明人： Zeev Sperber ,  Robert Valentine ,  Simcha Gochman

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885

摘要： A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The first decoder may decode a macroinstruction having SSE data type operands into a laminated micro-operation, and may generate unlamination information for the laminated micro-operation. The second decoder may generate from the laminated micro-operation and the unlamination information two or more micro-operations, where operands of the two or more micro-operations each correspond to a half of one of the SSE operands of the macroinstruction.

摘要翻译： 处理器可以包括用于将宏指令解码为微操作的指令解码器。 在一些实施例中，指令解码器可以包括第一解码器和第二解码器。 第一解码器可以将具有SSE数据类型操作数的宏指令解码为层叠微操作，并且可以生成层叠微操作的未分层信息。 第二解码器可以从层叠微操作和非分层信息生成两个或多个微操作，其中两个或多个微操作的操作数分别对应于宏指令的一个SSE操作数中的一个。

公开(公告)号：US10565283B2

公开(公告)日：2020-02-18

申请号：US13976766

申请日：2011-12-22

申请人： Seth Abraham ,  Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Zeev Sperber ,  Amit Gradstein

发明人： Seth Abraham ,  Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30 ,  G06F17/10

摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four consecutive non-negative integers in numerical order. In an aspect, the instruction does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location. Other methods, apparatus, systems, and instructions are disclosed.

公开(公告)号：US09658850B2

公开(公告)日：2017-05-23

申请号：US13976993

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30029 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

公开(公告)号：US09619236B2

公开(公告)日：2017-04-11

申请号：US13976992

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3802

摘要： An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

公开(公告)号：US09582464B2

公开(公告)日：2017-02-28

申请号：US13992229

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Mostafa Hagog ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

发明人： Elmoustapha Ould-Ahmed-Vall ,  Mostafa Hagog ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

IPC分类号： G06F7/38 ,  G06F9/302 ,  G06F15/78 ,  G06F9/30 ,  G06F7/544 ,  G06F9/38 ,  G06F7/50

CPC分类号： G06F9/3001 ,  G06F7/50 ,  G06F7/544 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3877 ,  G06F15/78 ,  G06F2207/5442

摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.

摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数的绝对差指令的单向量双块压缩和，绝对差（SAD）的双块压缩和，第一和第二 描述源操作数，立即数和操作码。

公开(公告)号：US20150261590A1

公开(公告)日：2015-09-17

申请号：US14214910

申请日：2014-03-15

申请人： Zeev Sperber ,  Robert Valentine ,  Offer Levy ,  Michael Mishaeli ,  Gal Ofir

发明人： Zeev Sperber ,  Robert Valentine ,  Offer Levy ,  Michael Mishaeli ,  Gal Ofir

IPC分类号： G06F11/07

CPC分类号： G06F11/079 ,  G06F11/0721 ,  G06F11/073

摘要： In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode stage to decode one or more instruction specifying: a set of memory operations, one or more register, and one or more memory address. One or more execution units, responsive to the one or more decoded instruction, generate said one or more memory address for the set of memory operations. Instruction execution logic records one or more fault suppress bits to indicate whether one or more portion of the set of memory operations are masked. Fault generation logic is suppressed from considering a memory fault corresponding to a faulting one of the set of memory operations when said faulting one of the set of memory operations corresponds to a portion of the set of memory operations that is indicated as masked by said one or more fault suppress bits.

摘要翻译： 在一些公开的实施例中，指令执行逻辑提供条件存储器故障辅助抑制。 处理器的一些实施例包括解码级，以对一个或多个指令进行解码，该指令指定：一组存储器操作，一个或多个寄存器和一个或多个存储器地址。 响应于一个或多个解码指令的一个或多个执行单元为该组存储器操作生成所述一个或多个存储器地址。 指令执行逻辑记录一个或多个故障抑制位以指示该组存储器操作中的一个或多个部分被屏蔽。 当所述一组存储器操作中的所述故障之一对应于由所述一组存储器操作屏蔽的所述一组存储器操作的一部分时，故障产生逻辑被抑制为考虑与所述一组存储器操作中的故障的一个存储器操作相对应的存储器故障， 更多的故障抑制位。

公开(公告)号：US20140208080A1

公开(公告)日：2014-07-24

申请号：US13997006

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Tal Uliel ,  Jesus Corbal ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Tal Uliel ,  Jesus Corbal ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30101 ,  G06F9/3001 ,  G06F9/30036

摘要： An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit(s) indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location.

摘要翻译： 描述了用于从源操作数到具有掩蔽的目的地操作数的下变频的装置和方法。 例如，根据一个实施例的方法包括以下操作：将从第一值下变频的源操作数值读取到下变换值并存储在目的位置; 读取存储在掩码寄存器中的每个掩码寄存器位，指示是否对源操作数值执行掩蔽操作或转换操作的掩码寄存器位; 如果屏蔽寄存器位指示要执行屏蔽操作，则执行指定的屏蔽操作并将掩蔽操作的结果存储在目的地位置中; 并且如果屏蔽寄存器位指示不执行屏蔽操作，则对源操作数值进行下变频并将下变频值存储在指定的目的地位置。

公开(公告)号：US20140059322A1

公开(公告)日：2014-02-27

申请号：US13996800

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L Toll ,  Mark J Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L Toll ,  Mark J Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F15/80

摘要： An apparatus and method are described for broadcasting from a general purpose source register to a destination vector register. For example, a method according to one embodiment includes the following operations: selecting data element position N within the destination vector register to be updated; broadcasting a set of data from the general purpose source register to data element position N within the destination vector register if a mask indicator is set to a first indication; and either copying zeroes to data element position N within the destination vector register or maintaining existing values stored within data element position N within the destination vector register if the mask indicator is set to a second indication.

摘要翻译： 描述了用于从通用源寄存器到目的地向量寄存器的广播的装置和方法。 例如，根据一个实施例的方法包括以下操作：选择要更新的目的地向量寄存器内的数据元素位置N; 如果将掩码指示符设置为第一指示，则将一组数据从通用源寄存器传送到目的地向量寄存器内的数据元素位置N; 并且如果掩模指示符被设置为第二指示，则将零值复制到目的地向量寄存器内的数据元素位置N，或者保持存储在目的地向量寄存器内的数据元素位置N内的现有值。

公开(公告)号：US20130326160A1

公开(公告)日：2013-12-05

申请号：US13487184

申请日：2012-06-02

申请人： Zeev Sperber ,  Robert Valentine ,  Guv Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

发明人： Zeev Sperber ,  Robert Valentine ,  Guv Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC分类号： G06F12/00

CPC分类号： G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

摘要翻译： 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码分散/收集指令并生成一组微操作，以及索引阵列以保存一组索引和相应的一组掩码元素。 有限状态机有助于收集操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 如果mask元素具有第一个值，则访问地址以加载相应的数据元素。 根据相应的注册位置的索引，将数据元素写入到目的地向量寄存器的寄存器位置。 响应于其相应负载的完成，对应的屏蔽元件的值从第一值改变为第二值。