公开(公告)号：US08972697B2

公开(公告)日：2015-03-03

申请号：US13487184

申请日：2012-06-02

申请人： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

发明人： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC分类号： G06F12/02

CPC分类号： G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

摘要翻译： 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码分散/收集指令并生成一组微操作，以及索引阵列以保存一组索引和相应的一组掩码元素。 有限状态机有助于收集操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 如果mask元素具有第一个值，则访问地址以加载相应的数据元素。 根据相应的注册位置的索引，将数据元素写入到目的地向量寄存器的寄存器位置。 响应于其相应负载的完成，对应的屏蔽元件的值从第一值改变为第二值。

公开(公告)号：US20140380338A1

公开(公告)日：2014-12-25

申请号：US13926089

申请日：2013-06-25

申请人： LEV MAKOVSKY ,  ZEEV SPERBER ,  EFRAIM ROTEM ,  NIR ROSENZWEIG ,  STANISLAV SHWARTSMAN ,  RAANAN SADE ,  IGOR YANOVER ,  GAVRI BERGER ,  TOMER WEINER ,  RON GABOR

发明人： LEV MAKOVSKY ,  ZEEV SPERBER ,  EFRAIM ROTEM ,  NIR ROSENZWEIG ,  STANISLAV SHWARTSMAN ,  RAANAN SADE ,  IGOR YANOVER ,  GAVRI BERGER ,  TOMER WEINER ,  RON GABOR

IPC分类号： G06F9/54

CPC分类号： G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

摘要： In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

公开(公告)号：US20160267009A1

公开(公告)日：2016-09-15

申请号：US14643354

申请日：2015-03-10

申请人： Oleg Margulis ,  Sumit Ahuja ,  Polychronis Xekalakis ,  Yongjun Park ,  Vineeth Mekkat ,  Igor Yanover ,  Sebastian Winkel ,  Ethan Schuchman

发明人： Oleg Margulis ,  Sumit Ahuja ,  Polychronis Xekalakis ,  Yongjun Park ,  Vineeth Mekkat ,  Igor Yanover ,  Sebastian Winkel ,  Ethan Schuchman

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F9/38 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/467 ,  G06F2212/1008 ,  G06F2212/452

摘要： A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.

摘要翻译： 描述了用于别名检测的处理器和方法。 例如，设备的一个实施例包括：重新排序逻辑以按照程序顺序接收一组读取和写入操作，并响应于重新排序读取和写入操作; 调整信息附加逻辑，用于将调整信息与所述一组读取和写入操作中的一个或多个相关联，其中对于读取操作，所述调整信息用于指示所述读取操作已绕过的写入操作的数量，并且对于写入操作，所述调整 信息是指示绕过了写入操作的多个读取操作; 以及无序处理逻辑，以确定重新排序的读取和写入操作的执行是否将导致至少部分地基于与所述一个或多个读取和写入相关联的调整信息的冲突。

公开(公告)号：US09411728B2

公开(公告)日：2016-08-09

申请号：US13994399

申请日：2011-12-23

申请人： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

发明人： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

IPC分类号： G06F13/00 ,  G06F12/08 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F12/0811 ,  G06F12/08 ,  G06F12/0844 ,  G06F12/0897 ,  G06F13/14 ,  G06F13/38

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.

摘要翻译： 根据本文公开的实施例，提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。 这种实施例中的数据缓冲器与数据总线可通信地接口，并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线，一个或多个控制位以指示各个数据缓冲器的状态，以及 与完整缓存行相关联的地址。 在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态和与相应无数据缓冲器相关联的高速缓存间传输线的地址。 在这样的实施例中，高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线，并且进一步将数据总线上的缓存间传输线写入低级缓存。

公开(公告)号：US20130326145A1

公开(公告)日：2013-12-05

申请号：US13994399

申请日：2011-12-23

申请人： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

发明人： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/08 ,  G06F12/0844 ,  G06F12/0897 ,  G06F13/14 ,  G06F13/38

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.

摘要翻译： 根据本文公开的实施例，提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。 这种实施例中的数据缓冲器与数据总线可通信地接口，并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线，一个或多个控制位以指示各个数据缓冲器的状态，以及 与完整缓存行相关联的地址。 在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态和与相应无数据缓冲器相关联的高速缓存间传输线的地址。 在这样的实施例中，高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线，并且进一步将数据总线上的缓存间传输线写入低级缓存。

公开(公告)号：US20150261270A1

公开(公告)日：2015-09-17

申请号：US14207074

申请日：2014-03-12

申请人： OMER VIKINSKI ,  IGOR YANOVER ,  GAVRI BERGER ,  GABI MALKA ,  ZEEV SPERBER

发明人： OMER VIKINSKI ,  IGOR YANOVER ,  GAVRI BERGER ,  GABI MALKA ,  ZEEV SPERBER

IPC分类号： G06F1/26 ,  G06F9/50

CPC分类号： G06F1/26 ,  G06F1/28 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/24

摘要： A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.

摘要翻译： 描述了用于执行执行单元端口的主动式节流的处理器和方法。 例如，处理器核心的一个实施例包括：处理器核心的执行阶段内的多个执行单元端口; 调度单元，对多个执行单元端口进行多个操作的执行; 以及主动节流逻辑，以将端口的操作的执行加速度限制到不会导致显着的电源下降的加速度水平。

公开(公告)号：US08516577B2

公开(公告)日：2013-08-20

申请号：US12887898

申请日：2010-09-22

申请人： Michael S. Bair ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

发明人： Michael S. Bair ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

IPC分类号： G06F21/00

CPC分类号： G06F9/526

摘要： In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，其将定时器与第一线程相关联，并且在完成第一线程之后防止第一线程执行存储器簇操作 原子记忆操作，直到预防窗口过去。 在一些实施例中，该方法可以通过与处理器的存储器执行单元相关联的调节逻辑执行。 描述和要求保护其他实施例。

公开(公告)号：US09626333B2

公开(公告)日：2017-04-18

申请号：US13977727

申请日：2012-06-02

申请人： Zeev Sperber ,  Robert Valentine ,  Shlomo Raikin ,  Stanislav Shwartsman ,  Gal Ofir ,  Igor Yanover ,  Guy Patkin ,  Levy Ofer

发明人： Zeev Sperber ,  Robert Valentine ,  Shlomo Raikin ,  Stanislav Shwartsman ,  Gal Ofir ,  Igor Yanover ,  Guy Patkin ,  Levy Ofer

IPC分类号： G06F9/00 ,  G06F15/78 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F15/7839 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3808 ,  G06F9/383

摘要： Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

公开(公告)号：US20120072984A1

公开(公告)日：2012-03-22

申请号：US12887898

申请日：2010-09-22

申请人： MICHAEL S. BAIR ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

发明人： MICHAEL S. BAIR ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

IPC分类号： G06F21/00

CPC分类号： G06F9/526

摘要： In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，其将定时器与第一线程相关联，并且在完成第一线程之后防止第一线程执行存储器簇操作 原子记忆操作，直到预防窗口过去。 在一些实施例中，该方法可以通过与处理器的存储器执行单元相关联的调节逻辑执行。 描述和要求保护其他实施例。

公开(公告)号：US20170286121A1

公开(公告)日：2017-10-05

申请号：US15089095

申请日：2016-04-01

申请人： Gur HILDESHEIM ,  Igor YANOVER ,  Stanislav SHWARTSMAN ,  Raanan SADE ,  Ron RAIS

发明人： Gur HILDESHEIM ,  Igor YANOVER ,  Stanislav SHWARTSMAN ,  Raanan SADE ,  Ron RAIS

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3836 ,  G06F9/3859

摘要： An apparatus and method are described for at-retirement re-execution of faulting operations. For example, one embodiment of a processor comprises: an out-of-order engine to schedule and dispatch operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory; a first circuit to determine whether a current load/store operation is at retirement; a second circuit to cause logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement, wherein upon detection of a fault condition associated with the load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers, the second circuit to cause the logging circuitry and/or fault registers to be inactive if the load/store operation has not be dispatched at retirement.