公开(公告)号：US20170185407A1

公开(公告)日：2017-06-29

申请号：US14998295

申请日：2015-12-26

申请人： Stanislav Shwartsman

发明人： Stanislav Shwartsman

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30043 ,  G06F12/0875 ,  G06F2212/452

摘要： An apparatus and method for detecting and eliminating loop-invariant instructions. For example, one embodiment of a method comprises: detecting a loop start; responsively setting the loop-invariant bit for each register entry in a register alias table; executing first N iterations of the loop and responsively clearing the loop-invariant bit of any register modified during the first N iterations of the loop; identifying one or more loop-invariant registers based on the status of the loop-invariant bit in the register alias table; identifying one or more loop-invariant instructions based on the loop-invariant registers; and propagating the identified loop-invariant instructions by storing the destination register's values in a physical register file for later reuse by other instructions.

公开(公告)号：US20150089280A1

公开(公告)日：2015-03-26

申请号：US14038334

申请日：2013-09-26

申请人： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

发明人： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

IPC分类号： G06F11/07

CPC分类号： G06F11/073 ,  G06F11/0793 ,  G06F11/08

摘要： Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

摘要翻译： 提供了同时处理多个数据错误的机制。 处理设备可以确定在存储器位置范围内的存储器位置中是否发生多个数据错误。 如果多个存储器位置在存储器位置的范围内，则处理设备可以继续恢复过程。 如果多个存储器位置中的一个位于存储器位置的范围之外，则处理设备可以停止恢复过程。

公开(公告)号：US20140122811A1

公开(公告)日：2014-05-01

申请号：US13664682

申请日：2012-10-31

申请人： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

发明人： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

IPC分类号： G06F12/08

CPC分类号： G06F12/121 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1032 ,  G06T1/20

摘要： A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed.

摘要翻译： 处理器包括执行指令的核心和耦合到核心并且具有多个条目的高速缓存存储器。 高速缓冲存储器的每个条目可以包括包括多个数据存储部分的数据存储部分，每个数据存储部分存储对应的数据部分。 每个条目还可以包括用于存储多个部分修改指示符的元数据存储器，每个部分修改指示符对应于数据存储部分之一。 每个部分修改指示符用于指示存储在相应的数据存储部分中的数据部分是否已被修改，而与条目的高速缓存一致性状态信息无关。 其他实施例被描述为所要求保护的。

公开(公告)号：US20170286121A1

公开(公告)日：2017-10-05

申请号：US15089095

申请日：2016-04-01

申请人： Gur HILDESHEIM ,  Igor YANOVER ,  Stanislav SHWARTSMAN ,  Raanan SADE ,  Ron RAIS

发明人： Gur HILDESHEIM ,  Igor YANOVER ,  Stanislav SHWARTSMAN ,  Raanan SADE ,  Ron RAIS

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3836 ,  G06F9/3859

摘要： An apparatus and method are described for at-retirement re-execution of faulting operations. For example, one embodiment of a processor comprises: an out-of-order engine to schedule and dispatch operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory; a first circuit to determine whether a current load/store operation is at retirement; a second circuit to cause logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement, wherein upon detection of a fault condition associated with the load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers, the second circuit to cause the logging circuitry and/or fault registers to be inactive if the load/store operation has not be dispatched at retirement.

公开(公告)号：US20160179545A1

公开(公告)日：2016-06-23

申请号：US14581268

申请日：2014-12-23

申请人： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

发明人： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

IPC分类号： G06F9/38

CPC分类号： G06F9/384 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30116 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3891

摘要： A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

摘要翻译： 处理器包括核心，存储器子系统，预测器模块和存储器重命名模块。 预测器模块可以包括用于识别存储指令和加载指令之间的依赖性的第一逻辑，以及基于所识别的依赖关系将存储器重命名（MRN）寄存器分配给存储指令和加载指令的第二逻辑。 此外，存储器重命名模块可以包括第三逻辑，用于基于所分配的MRN寄存器将与存储指令相关联的第一逻辑寄存器中的信息直接复制到与加载指令相关联的第二逻辑寄存器。

公开(公告)号：US20130326160A1

公开(公告)日：2013-12-05

申请号：US13487184

申请日：2012-06-02

申请人： Zeev Sperber ,  Robert Valentine ,  Guv Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

发明人： Zeev Sperber ,  Robert Valentine ,  Guv Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC分类号： G06F12/00

CPC分类号： G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

摘要翻译： 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码分散/收集指令并生成一组微操作，以及索引阵列以保存一组索引和相应的一组掩码元素。 有限状态机有助于收集操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 如果mask元素具有第一个值，则访问地址以加载相应的数据元素。 根据相应的注册位置的索引，将数据元素写入到目的地向量寄存器的寄存器位置。 响应于其相应负载的完成，对应的屏蔽元件的值从第一值改变为第二值。

公开(公告)号：US20110208918A1

公开(公告)日：2011-08-25

申请号：US12978513

申请日：2010-12-24

申请人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

发明人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/30032 ,  G06F9/3824 ,  G06F9/384 ,  Y02D10/13

摘要： Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

摘要翻译： 描述与硬件移动消除和/或下一页预取相关的方法和装置。 在一些实施例中，逻辑可以基于存储的数据提供硬件移动消除。 在一个实施例中，公开了下一页预取器。 还描述和要求保护其他实施例。

公开(公告)号：US09405545B2

公开(公告)日：2016-08-02

申请号：US13993508

申请日：2011-12-30

申请人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

发明人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

IPC分类号： G06F12/08 ,  G06F9/38

CPC分类号： G06F9/3814 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0808 ,  G06F12/0862 ,  G06F2212/6028 ,  G06F2212/62

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

摘要翻译： 根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。 这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

公开(公告)号：US08972697B2

公开(公告)日：2015-03-03

申请号：US13487184

申请日：2012-06-02

申请人： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

发明人： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC分类号： G06F12/02

CPC分类号： G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

摘要翻译： 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码分散/收集指令并生成一组微操作，以及索引阵列以保存一组索引和相应的一组掩码元素。 有限状态机有助于收集操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 如果mask元素具有第一个值，则访问地址以加载相应的数据元素。 根据相应的注册位置的索引，将数据元素写入到目的地向量寄存器的寄存器位置。 响应于其相应负载的完成，对应的屏蔽元件的值从第一值改变为第二值。

公开(公告)号：US20140380338A1

公开(公告)日：2014-12-25

申请号：US13926089

申请日：2013-06-25

申请人： LEV MAKOVSKY ,  ZEEV SPERBER ,  EFRAIM ROTEM ,  NIR ROSENZWEIG ,  STANISLAV SHWARTSMAN ,  RAANAN SADE ,  IGOR YANOVER ,  GAVRI BERGER ,  TOMER WEINER ,  RON GABOR

发明人： LEV MAKOVSKY ,  ZEEV SPERBER ,  EFRAIM ROTEM ,  NIR ROSENZWEIG ,  STANISLAV SHWARTSMAN ,  RAANAN SADE ,  IGOR YANOVER ,  GAVRI BERGER ,  TOMER WEINER ,  RON GABOR

IPC分类号： G06F9/54

CPC分类号： G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

摘要： In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。