Wafer level chip scale package with reduced stress on solder balls
    21.
    发明授权
    Wafer level chip scale package with reduced stress on solder balls 有权
    晶圆级芯片级封装,焊球应力减小

    公开(公告)号:US08373282B2

    公开(公告)日:2013-02-12

    申请号:US13162394

    申请日:2011-06-16

    IPC分类号: H01L23/52 H01L23/48 H01L29/40

    摘要: A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.

    摘要翻译: 一种结构包括半导体衬底上的金属焊盘,具有金属焊盘上方的一部分的钝化层以及钝化层上的第一聚酰亚胺层,其中第一聚酰亚胺层具有第一厚度和第一杨氏模量。 后钝化互连(PPI)包括在第一聚酰亚胺层之上的第一部分,以及延伸到钝化层和第一聚酰亚胺层中的第二部分。 PPI电耦合到金属垫。 第二个聚酰亚胺层位于PPI之上。 第二聚酰亚胺层具有第二厚度和第二杨氏模量。 厚度比和杨氏模量比中的至少一个大于1.0,其中厚度比是第一厚度与第二厚度的比率,杨氏模量比是第二杨氏模量与第一杨氏模量之比 模数。