公开(公告)号：US20170212835A1

公开(公告)日：2017-07-27

申请号：US15098965

申请日：2016-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaohong Hu ,  Hongzhong Zheng

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F13/16 ,  Y02D10/13

Abstract: A computing system includes: a storage component including a volatile-memory device and a non-volatile memory device configured to enable persistent storage of information along with block-oriented mass storage of information; and a controller component, coupled to the storage component, configured to implement a smart memory driver configured to dynamically manage the volatile-memory device including managing a persistent memory (PM) portion, a hardware cache (HWC) portion, a block window (BW) portion, or a combination thereof within the volatile-memory device.

公开(公告)号：US20160011940A1

公开(公告)日：2016-01-14

申请号：US14606334

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaohong Hu ,  Uksong Kang ,  Hongzhong Zheng

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/1012 ,  G06F11/1024 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/108 ,  G06F2211/1057

Abstract: Exemplary embodiments provide a tiered error correction code (ECC) Chipkill system, comprising: a device ECC incorporated into at least a portion of a plurality of memory devices that corrects n-bit memory device-level failures in the respective memory device, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and a system-level ECC device external to the plurality of memory devices is responsive to receiving the memory device failure signal to correct the memory device failure based on a system ECC parity.

Abstract translation: 示例性实施例提供了一种分层纠错码（ECC）Chipkill系统，包括：整合到多个存储器装置的至少一部分中的装置ECC，其校正相应存储装置中的n位存储装置级故障，并发送 当任何存储器件级故障大于n位且超出器件ECC器件的校正能力时，存储器件故障信号; 并且多个存储器设备外部的系统级ECC设备响应于基于系统ECC奇偶校验接收存储器件故障信号以校正存储器件故障。

公开(公告)号：US20160011817A1

公开(公告)日：2016-01-14

申请号：US14569017

申请日：2014-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Liang Yin ,  Chaohong Hu

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F3/0679 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/109

Abstract: A computing system includes: a memory computing block configured to: identify a partial data computing (PDC) command, a data mask, a partial data, or a combination thereof based on decoding a data packet, compute a computation result for identifying a portion of a read data to be modified according to the PDC command, the data mask, the partial data, or a combination thereof, generate a merge result based on modifying the portion of the read data according to the computation result, and a memory interface, coupled to the memory computing block, configured to transmit the merge result.

Abstract translation: 计算系统包括：存储器计算块，被配置为：基于解码数据分组来识别部分数据计算（PDC）命令，数据掩码，部分数据或其组合，计算用于识别 根据PDC命令，数据掩码，部分数据或其组合要修改的读取数据，根据计算结果，修改读取数据的部分，生成合并结果，以及存储器接口 到存储器计算块，被配置为发送合并结果。