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    COMPUTING SYSTEM WITH BUFFER AND METHOD OF OPERATION THEREOF
    3.
    发明申请
    COMPUTING SYSTEM WITH BUFFER AND METHOD OF OPERATION THEREOF 有权
    具有缓冲器的计算系统及其操作方法

    公开(公告)号：US20160188224A1

    公开(公告)日：2016-06-30

    申请号：US14735765

    申请日：2015-06-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Liang Yin ,  Zvi Guz

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/4059

    Abstract: A computing system includes: a write buffer block configured to: receive a data in a write buffer entry for staging the data prior to transferring the data to a storage cell, determine a validity identification of the data for a buffer entry address of the write buffer entry, store the data based on the validity identification to the write buffer entry, and a memory computing block, coupled to the write buffer block, configured to read the data for accessing the write buffer block.

    Abstract translation: 一种计算系统包括：写入缓冲器块，被配置为：在将数据传送到存储单元之前，在写入缓冲器条目中接收数据以暂存数据，确定写入缓冲器的缓冲器入口地址的数据的有效性标识 输入，将基于有效性标识的数据存储到写缓冲器条目，以及耦合到写缓冲器块的存储器计算块，其被配置为读取用于访问写缓冲器块的数据。

    Memory devices and modules
    9.
    发明授权
    Memory devices and modules 有权

    公开(公告)号：US10002043B2

    公开(公告)日：2018-06-19

    申请号：US14678968

    申请日：2015-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chaohong Hu ,  Liang Yin ,  Hongzhong Zheng ,  Uksong Kang

    IPC: G06F11/00 ,  G06F11/10

    CPC classification number: G06F11/10 ,  G06F11/1008 ,  G06F11/1076

    Abstract: A memory device includes a memory, a data interface, an error interface and a controller. The data interface communicates data to and from the memory device through an external main memory path. The error interface communicates error information from the memory device through an external system control path and that is separate from the main memory path. The controller is coupled to the data interface, the error interface, and the memory. The controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the memory and generates corrected data by encoding data written to the memory and decoding data read from the memory, generates error information, transmits the corrected data through the data interface, and transmits the error information through the error interface. The ECC controller records the error information in response to the ECC engine.

    High performance transaction-based memory systems
    10.
    发明授权
    High performance transaction-based memory systems 有权

    公开(公告)号：US09904635B2

    公开(公告)日：2018-02-27

    申请号：US14959773

    申请日：2015-12-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mu-Tien Chang ,  Hongzhong Zheng ,  Liang Yin

    IPC: G06F13/14 ,  G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/1668 ,  G06F13/4068

    Abstract: A memory system includes a master controller, an interface with a host computer, and a link bus configured to couple with a slave controller. The master controller includes an address mapping decoder, a transaction queue, and a scheduler. The address mapping decoder is configured to decode address mapping information of a memory device coupled to the slave controller. The scheduler of the master controller is configured to reorder memory transaction requests received from the host computer in the transaction queue using the address mapping information of the memory device. The memory system employs an extended open page policy based on the pending memory transaction requests in the transaction queue of the master controller.

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