中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

35 records (took 0.025 seconds)

    LOW DENSITY PARITY CHECK DECODER AND STORAGE DEVICE
    21.
    发明公开
    LOW DENSITY PARITY CHECK DECODER AND STORAGE DEVICE 审中-公开

    公开(公告)号：US20230163785A1

    公开(公告)日：2023-05-25

    申请号：US17878431

    申请日：2022-08-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangseok Lee ,  Geunyeong Yu ,  Youngjun Hwang ,  Hongrak Son ,  Junho Shin ,  Bohwan Jun ,  Hyunseung Han

    IPC: H03M13/11

    CPC classification number: H03M13/1134 ,  H03M13/112

    Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

    Storage controller, system including the same, and method of operating the same
    22.
    发明授权
    Storage controller, system including the same, and method of operating the same 有权

    公开(公告)号：US11632232B2

    公开(公告)日：2023-04-18

    申请号：US17167203

    申请日：2021-02-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehun Jang ,  Youngsik Moon ,  Wijik Lee ,  Hongrak Son

    IPC: H04L9/00 ,  H04L9/08

    Abstract: A client system includes a client-side host device, and a client-side storage device including a storage controller and a storage memory. The storage controller includes a host interface, a processor configured to control a read operation and a write operation for the storage memory, and a homomorphic encryption and decryption accelerator configured to, based on receiving a read request from the client-side host device, perform homomorphic encryption on first plaintext data that is read from the storage memory, to generate first homomorphic ciphertext data, and provide the first homomorphic ciphertext data to the client-side host device through the host interface, and based on receiving a write request from the client-side host device, perform homomorphic decryption on second homomorphic ciphertext data that is received through the host interface, to generate second plaintext data, and write the second plaintext data in the storage memory.

    Memory device storing parity and memory system including the same
    23.
    发明授权
    Memory device storing parity and memory system including the same 有权

    公开(公告)号：US11562803B2

    公开(公告)日：2023-01-24

    申请号：US17244195

    申请日：2021-04-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjun Hwang ,  Heeyoul Kwak ,  Bohwan Jun ,  Hongrak Son ,  Dongmin Shin ,  Geunyeong Yu

    IPC: G11C16/10 ,  G11C29/42 ,  G11C16/26 ,  G11C29/44 ,  G11C29/00

    Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.

    Stacked neuromorphic devices and neuromorphic computing systems
    24.
    发明授权
    Stacked neuromorphic devices and neuromorphic computing systems 有权

    公开(公告)号：US11531871B2

    公开(公告)日：2022-12-20

    申请号：US16854942

    申请日：2020-04-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Geunyeong Yu ,  Chanho Yoon ,  Pilsang Yoon

    IPC: G06N3/04 ,  H01L25/18 ,  G06N3/063 ,  H01L25/065

    Abstract: A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.

    STORAGE CONTROLLER, STORAGE SYSTEM AND METHOD OF OPERATING THE SAME
    25.
    发明申请
    STORAGE CONTROLLER, STORAGE SYSTEM AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20220365847A1

    公开(公告)日：2022-11-17

    申请号：US17816554

    申请日：2022-08-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanbyeul NA ,  Jaehun Jang ,  Hongrak Son

    IPC: G06F11/10 ,  G06F11/07

    Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.

    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE
    29.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE 有权

    公开(公告)号：US20240402941A1

    公开(公告)日：2024-12-05

    申请号：US18644558

    申请日：2024-04-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehun Jang ,  Sumin Kim ,  Jiwon Seo ,  Mankeun Seo ,  Hongrak Son ,  Dongmin Shin

    IPC: G06F3/06

    Abstract: A memory device includes first and second memory cell arrays each including a plurality of memory cells, a page buffer circuit configured to read first soft decision data including a plurality of sub-segments from the first memory cell array, and a compression circuit configured to perform a first compression operation of generating a first compression segment including a number of position values less than or equal to a first reference number, on each of a plurality of partial segments included in one of the plurality of sub-segments and sequentially perform a plurality of compression operations, which is subsequent to the first compression operation, of generating a next compression segment including a number of position values, which are less than or equal to a reference number corresponding to each compression operation, of position values included in two or more previous compression segments in each compression operation.

    ECC DECODER AND MEMORY CONTROLLER INCLUDING THE SAME
    30.
    发明公开
    ECC DECODER AND MEMORY CONTROLLER INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240143442A1

    公开(公告)日：2024-05-02

    申请号：US18495156

    申请日：2023-10-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Soonyoung Kang ,  Yongsung Kil ,  Jaehong Kim ,  Hongrak Son

    IPC: G06F11/10 ,  G06F11/07

    CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1048

    Abstract: A memory controller includes a processor, which is configured to determine one of a first operation mode and a second operation mode as an operation mode based on a lifespan or retention of a memory device. The processor is configured to transmit to the memory device, a read command for obtaining hard decision (HD) data and a first piece of SD data during a time period of a single read, or a read command for obtaining a second piece of SD data from a plurality of reads. A decoding circuit is configured to perform iterative decoding based on the first piece of SD data or the second piece of SD data. The first operation mode is for sequentially transmitting the coarse SD read command and the fine SD read command to the memory device, whereas the second operation mode is for transmitting the fine SD read command.

Patent Agency Ranking