公开(公告)号：US20240143442A1

公开(公告)日：2024-05-02

申请号：US18495156

申请日：2023-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soonyoung Kang ,  Yongsung Kil ,  Jaehong Kim ,  Hongrak Son

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1048

Abstract: A memory controller includes a processor, which is configured to determine one of a first operation mode and a second operation mode as an operation mode based on a lifespan or retention of a memory device. The processor is configured to transmit to the memory device, a read command for obtaining hard decision (HD) data and a first piece of SD data during a time period of a single read, or a read command for obtaining a second piece of SD data from a plurality of reads. A decoding circuit is configured to perform iterative decoding based on the first piece of SD data or the second piece of SD data. The first operation mode is for sequentially transmitting the coarse SD read command and the fine SD read command to the memory device, whereas the second operation mode is for transmitting the fine SD read command.

公开(公告)号：US20240128986A1

公开(公告)日：2024-04-18

申请号：US18318874

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： YongSung KIL ,  Soonyoung Kang ,  Hong Rak Son ,  Kangseok Lee

IPC: H03M13/11 ,  G06F11/10

CPC classification number: H03M13/1177 ,  G06F11/1004

Abstract: Disclosed is a storage device which includes a nonvolatile memory device, and a memory controller that performs a read operation on the nonvolatile memory device and performs an error correction operation on data read in the read operation. In the error correction operation, the memory controller estimates an error rate of the read data, and determines whether to perform a read retry operation based on the estimated error rate.

公开(公告)号：US20240427520A1

公开(公告)日：2024-12-26

申请号：US18737403

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonyoung Kang ,  Dongmin Shin

IPC: G06F3/06

Abstract: An example memory system includes a memory device and a memory controller. The memory device is configured to read, from a memory cell array, hard decision data based on a hard read voltage and first soft decision data based on first soft read voltages obtained based on the hard read voltage and a first voltage offset, generate a first compressed sub-segment based on encoding a position of a bit having a first value into a position value for each of first soft decision sub-segments in the first soft decision data, and output first compressed data including first compressed sub-segments. The memory controller is configured to receive the first compressed data, count the number of position values in each of the first compressed sub-segments, and provide, to the memory device based on the counted number, a command to request a change of a voltage offset and a recompression operation.

公开(公告)号：US20240079073A1

公开(公告)日：2024-03-07

申请号：US18320318

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： YongSung Kil ,  Soonyoung Kang ,  Hong Rak Son ,  Kangseok Lee

IPC: G11C29/02 ,  G11C11/408 ,  G11C29/52

CPC classification number: G11C29/021 ,  G11C11/4087 ,  G11C29/52

Abstract: Disclosed is a method of operating a storage controller which is configured to communicate with a non-volatile memory device. The method includes receiving count data from the non-volatile memory device, determining a pre-read voltage based on the count data, sending a pre-read request using the pre-read voltage to the non-volatile memory device, receiving pre-read data from the non-volatile memory device responsive to sending the pre-read request, calculating a decoding value corresponding to the pre-read data, and generating read voltage information based on the count data and the decoding value, and the decoding value predicts an error voltage of the pre-read data.

公开(公告)号：US20250014647A1

公开(公告)日：2025-01-09

申请号：US18408126

申请日：2024-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minuk KIM ,  Soonyoung Kang ,  Kwanwoo Noh ,  Dong-Min Shin

IPC: G11C16/10 ,  G11C16/08

Abstract: A storage device includes a nonvolatile memory device including a plurality of first memory cells coupled to a first wordline and a plurality of second memory cells coupled to a second wordline, the first wordline and the second wordline being adjacent to each other, and a storage controller configured to control the nonvolatile memory device. The storage controller is further configured to encode data to be programmed into the plurality of second memory cells, based on a program state of each of the plurality of first memory cells, and encode the data to be programmed into the second wordline such that a first portion of the data to be written into a first portion of the plurality of second memory cells satisfies a first condition, and a second portion of the data to be written into a second portion of the plurality of second memory cells satisfies a second condition.