公开(公告)号：US11036629B2

公开(公告)日：2021-06-15

申请号：US16729198

申请日：2019-12-27

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0808 ,  G06F11/07 ,  G06F11/30 ,  G06F12/0882

Abstract: In accordance with an embodiment of the present disclosure, a method of a controller for controlling a nonvolatile memory device including a plurality of data storage regions may include: determining, in response to a first copy event of receiving from a host a command instructing copy of data from a first logical address into a second logical address, whether a second copy event of copying the data from a first data storage region having a first physical address mapped to the first logical address into a data storage region having another physical address will occur; and in response to determining that the second copy event will not occur, changing a logical address mapped to the first physical address from the first logical address to the second logical address and invalidating the first logical address.

公开(公告)号：US10908836B2

公开(公告)日：2021-02-02

申请号：US16597287

申请日：2019-10-09

Applicant: Sk hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06

Abstract: A memory system includes a memory device comprising a plurality of planes and a controller suitable for controlling the memory device. The controller may include a processor suitable for determining at least one busy plane and at least one idle plane among the plurality of planes in response to a host command, and controlling the memory device such that the busy plane performs an operation associated with the host command and the idle plane performs an operation of erasing a complete dirty block in the idle plane. The busy plane and the idle plane may operate in parallel in response to control of the processor.

公开(公告)号：US12019891B2

公开(公告)日：2024-06-25

申请号：US17728921

申请日：2022-04-25

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06 ,  G06F16/901

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0673 ,  G06F16/9024

Abstract: Embodiments of the present disclosure relate to a memory controller and operating method thereof. According to embodiments of the present disclosure, the memory controller may generate a fused linked list which includes information of a plurality of write commands received from a host and a plurality of synchronization commands requesting a synchronization operation, and control the synchronization operation for one or more of the plurality of write commands based on the fused linked list.

公开(公告)号：US11941246B2

公开(公告)日：2024-03-26

申请号：US17506414

申请日：2021-10-20

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: Disclosed are a data processing system comprising: a memory system for providing a host with a memory map segment including map pieces; and the host for storing the memory map segment as a host map segment and converting a logical address into a physical address using the host map segment. The memory system stores changed map pieces in a map cache, inserts the changed map pieces in a response to a first command, and provides the host with the response. The host updates the host map segment based on the changed map pieces. When a read command includes a logical address and a physical address, the memory system accesses a memory device using the physical address of the read command according to whether the logical address of the read command is stored in the map cache.

公开(公告)号：US11841805B2

公开(公告)日：2023-12-12

申请号：US17877135

申请日：2022-07-29

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/123 ,  G06F9/30 ,  G06F12/1027 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/123 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0658 ,  G06F3/0659 ,  G06F9/30043 ,  G06F12/0246 ,  G06F12/1027 ,  G06F3/0679

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a host configured to generate and output a host command and a host address and to receive and store host map data, a controller configured to store map data, generate an internal command in response to the host command, and map the host address to an internal address based on the map data, and a memory device configured to perform an operation in response to the internal command and the internal address, wherein the controller is configured to load, when the map data corresponding to the host address is not stored in the controller, new map data into a map data storage area storing map data that is identical to the host map data.

公开(公告)号：US11720276B2

公开(公告)日：2023-08-08

申请号：US17336554

申请日：2021-06-02

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory system includes a storage medium and a controller. The storage medium includes a plurality of physical regions. The controller maps logical regions which are configured by a host device, to the physical regions, and performs in response to a write request for a target logical region, a write operation on a physical region mapped to the target logical region. The controller updates in response to the write request, a write status corresponding to the target logical region within a write status table.

公开(公告)号：US11609710B2

公开(公告)日：2023-03-21

申请号：US17177722

申请日：2021-02-17

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06 ,  G06F12/10

Abstract: A data processing system may include: a host including a command queue including a plurality of command storage areas, and configured to store summary information of a second command among a plurality of commands in a reserved storage area of a command storage area, among the plurality of command storage areas, in which a first command among the plurality of commands being a previous command to the second command is stored, when inserting the second command into the command queue; and a data storage device configured to fetch the first command from the command queue and store the fetched first command, according to a new command notification received from the host.

公开(公告)号：US11526438B2

公开(公告)日：2022-12-13

申请号：US17002210

申请日：2020-08-25

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/02 ,  G06F12/0891 ,  G06F12/0882

Abstract: An operation method of a controller, comprising: selecting a target super block, on which garbage collection (GC) is to be performed, among a plurality of super blocks which are completely programmed, based on a first valid page count of each of the super blocks when a determination to perform GC is made; selecting a first target block among a plurality of memory blocks in the target super block based on a second valid-page decrease amount of each of the memory blocks; and performing a first copy operation on valid pages in the first target block.

公开(公告)号：US11429538B2

公开(公告)日：2022-08-30

申请号：US16455961

申请日：2019-06-28

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/1009 ,  G06F12/123 ,  G06F9/30 ,  G06F12/1027 ,  G06F12/02 ,  G06F3/06

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a host configured to generate and output a host command and a host address and to receive and store host map data, a controller configured to store map data, generate an internal command in response to the host command, and map the host address to an internal address based on the map data, and a memory device configured to perform an operation in response to the internal command and the internal address, wherein the controller is configured to load, when the map data corresponding to the host address is not stored in the controller, new map data into a map data storage area storing map data that is identical to the host map data.

公开(公告)号：US11144246B2

公开(公告)日：2021-10-12

申请号：US16670562

申请日：2019-10-31

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06

Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks and a controller configured to control the nonvolatile memory device. The controller determines, as an available bad block, a memory block having data storage reliability equal to or greater than a first reference value, included in the plurality of memory blocks, determines write data to be stored in the nonvolatile memory device as first data which is required for the memory system to normally operate or second data which does not correspond to the first data, and allocate the write data determined as the second data to the available bad block. The nonvolatile memory device performs a write operation of storing the second data in the available bad block.