公开(公告)号：US11301174B2

公开(公告)日：2022-04-12

申请号：US16904178

申请日：2020-06-17

Applicant: SK hynix Inc.

Inventor： Hyun Tae Kim ,  Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/06

Abstract: A memory system, a memory controller and a method for operating the memory system. The memory system manages a hot data pool and a cold data pool, each of which includes at least one among a plurality of memory blocks, writes read only data to the cold data pool, and controls the hot data pool and the cold data pool in garbage collection and wear leveling, thereby classifying data, less frequently updated, into cold data and improving the performance of garbage collection and wear leveling.

公开(公告)号：US11301150B2

公开(公告)日：2022-04-12

申请号：US16698296

申请日：2019-11-27

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F12/10 ,  G06F3/06 ,  G06F12/1009

Abstract: The present technology relates to an electronic device. A memory controller according to the present technology has improved map update performance. The memory controller controls a memory device that stores logical to physical map data indicating a mapping relationship between a logical address and a physical address of data. The memory controller includes a map data storage and a map data manager. The map data storage stores physical to logical (P2L) map data generated based on a logical address corresponding to a request received from a host. The map data manager performs a map update operation for the L2P map data by using some of an entire P2L map data stored in the map data storage, according to an amount of the P2L map data stored in the map data storage.

公开(公告)号：US11995323B2

公开(公告)日：2024-05-28

申请号：US17984484

申请日：2022-11-10

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory controller includes a data detection circuit configured to detect, when power is supplied after a sudden power-off (SPO), a lost write sequence index “M” among the plural write sequence indexes, and detect first data corresponding to a write sequence index “M−1” and second data corresponding to a write sequence index “M+1”; a barrier decision circuit configured to determine, based on whether first barrier information of the first data and second barrier information of the second data are identical with each other, whether a barrier request for the first data has been received from a host; and a data recovery operation determination circuit configured to determine whether to perform a recovery operation on target data corresponding to the write sequence index “M+1” and thereafter based on whether the barrier request for the first data has been received.

公开(公告)号：US11922048B2

公开(公告)日：2024-03-05

申请号：US17148116

申请日：2021-01-13

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12

Abstract: A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.

公开(公告)号：US11775214B2

公开(公告)日：2023-10-03

申请号：US17338246

申请日：2021-06-03

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may fetch a first command from the host into a command queue, suspend execution of the first command when receiving a lock request for the first command from the host, and resume the execution of the first command when receiving an unlock request for the first command or after the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request.

公开(公告)号：US11561725B2

公开(公告)日：2023-01-24

申请号：US17362289

申请日：2021-06-29

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/06 ,  G06F12/0802

Abstract: Embodiments of the present disclosure relate to a system and an operating method thereof. According to embodiments of the present disclosure, a memory system may transmit a first type response indicating that first data has been cached in a cache to the host when receiving a first command requesting to write the first data from the host, and may transmit a second type response indicating success or failure of an operation of storing the first data in the memory device to the host after transmitting the first type response to the host. Further, the host may delete the first data from a write buffer after the operation of storing the first data in the memory device succeeds.

公开(公告)号：US11543986B2

公开(公告)日：2023-01-03

申请号：US17304076

申请日：2021-06-14

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F3/06

Abstract: An electronic system includes a file system configured to assign logical block addresses corresponding to consecutive pieces of data sets of segments in a plurality of zones. The electronic system also includes a memory device including a plurality of memory blocks, and a memory controller configured to map the logical block addresses to physical block addresses corresponding to consecutive pages in the plurality of memory blocks to program the consecutive pieces of data to the consecutive pages in the plurality of memory blocks. The file system is configured to assign new logical block addresses corresponding to consecutive pieces of a data file to invalid segments in the plurality of zones.

公开(公告)号：US11422892B2

公开(公告)日：2022-08-23

申请号：US17149314

申请日：2021-01-14

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F11/10 ,  G06F12/109

Abstract: A data storage apparatus is provided to include a storage including a main data region for storing first data and a spare region for storing second data indicating attributes of the first data; and a controller in communication with a host and configured to control the storage based on a request from the host, wherein the controller comprises: a first error check and correction (ECC) engine configured to perform an error correction on the first data stored in the main data region of the storage; and a second ECC engine configured to perform an error correction on the second data stored in the spare region of the storage.

公开(公告)号：US11294587B2

公开(公告)日：2022-04-05

申请号：US16659292

申请日：2019-10-21

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F3/06

Abstract: A data storage device includes a memory device and a controller. The memory device includes a rare open block that stores data corresponding to a re-allocated invalid logical address and a normal open block that stores data corresponding to a newly allocated free logical address. The controller determines whether to store write data in the rare open block or the normal open block based on information included in a write command received from a host, and controls the memory device to store the write data in the rare open block or the normal open block according to a result of the determination.

公开(公告)号：US11237954B2

公开(公告)日：2022-02-01

申请号：US16895019

申请日：2020-06-08

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/02 ,  G06F12/06 ,  G06F1/14 ,  G06F1/12 ,  G06F12/0873

Abstract: Provided herein may be a controller and a data storage system having the controller. The controller may include a mapping time generator configured to generate a first mapping time at which a logical block address and a physical block address are mapped to each other, an internal memory configured to store first address mapping information including an address map, and the first mapping time, a host interface configured to transmit the first address mapping information to a host, and receive second address mapping information from the host, and a central processing unit configured to generate the address map, store the first address mapping information in the internal memory, compare a second mapping time included in the second address mapping information with the first mapping time, and select a read mode based on a result of the comparison.