DELAY CONTROL CIRCUIT AND MEMORY DEVICE HAVING THE SAME

    公开(公告)号:US20200321039A1

    公开(公告)日:2020-10-08

    申请号:US16657196

    申请日:2019-10-18

    Applicant: SK hynix Inc.

    Abstract: A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.

    INPUT/OUTPUT CIRCUIT, MEMORY DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF

    公开(公告)号:US20200051600A1

    公开(公告)日:2020-02-13

    申请号:US16357523

    申请日:2019-03-19

    Applicant: SK hynix Inc.

    Inventor: Jin Ha HWANG

    Abstract: An input/output circuit for use in a memory includes: a data pattern detector for outputting an up resistance control code and a down resistance control code according to whether the pattern of consecutively input data is a consecutively varied pattern or an inconsecutively varied pattern; and an output circuit for controlling resistance in response to the up resistance control code and the down resistance control code, and amplifying the data and then outputting the amplified data to an input/output pad.

    DATA OUTPUT BUFFER AND MEMORY DEVICE HAVING THE SAME

    公开(公告)号:US20190371381A1

    公开(公告)日:2019-12-05

    申请号:US16253827

    申请日:2019-01-22

    Applicant: SK hynix Inc.

    Abstract: The present disclosure relates to a data out buffer and a memory device having the same. The data out buffer includes a pull-up main driver, coupled between a power supply terminal and an output terminal, configured to output data of a high level; and a pull-down main driver, coupled between the output terminal and a ground terminal, configured to output data of a low level, wherein the pull-up main driver comprises a main pull-up transistor of a first type; and a plurality of first trim transistors, each of a second type.

    DATA OUTPUT BUFFER
    24.
    发明申请
    DATA OUTPUT BUFFER 审中-公开

    公开(公告)号:US20190279691A1

    公开(公告)日:2019-09-12

    申请号:US16166773

    申请日:2018-10-22

    Applicant: SK hynix Inc.

    Inventor: Jin Ha HWANG

    Abstract: A data output buffer includes: a pull-up pre driver configured to output pull-up data by reversing received data, and output up-code for adjusting a swing width of the received data; a pull-down pre driver configured to output pull-down data by reversing the received data, and output a down-code for adjusting the swing width of the received data; a pull-up main driver configured to output first data having a value of logic high according to the pull-up data, and adjust a swing width of the first data according to the up-code; and a pull-down main driver configured to output second data having a value of logic low according to pull-down data, and adjust a swing width of the second data according to the down-code.

    BUFFER CIRCUIT CAPABLE OF IMPROVING AMPLIFICATION PERFORMANCE
    25.
    发明申请
    BUFFER CIRCUIT CAPABLE OF IMPROVING AMPLIFICATION PERFORMANCE 有权
    缓冲电路可提高放大性能

    公开(公告)号:US20160164465A1

    公开(公告)日:2016-06-09

    申请号:US14666414

    申请日:2015-03-24

    Applicant: SK hynix Inc.

    Abstract: A buffer circuit may include an amplification reference voltage generation unit and an amplification unit. The amplification reference voltage generation unit may generate an amplification reference voltage. The amplification reference voltage generation unit configured to change a level of the amplification reference voltage based on a level of an output signal. The amplification unit may generate the output signal by differentially amplifying an input signal and the amplification reference voltage.

    Abstract translation: 缓冲电路可以包括放大参考电压产生单元和放大单元。 放大参考电压产生单元可以产生放大参考电压。 所述放大基准电压生成部基于输出信号的电平来变更所述放大基准电压的电平。 放大单元可以通过差分放大输入信号和放大参考电压来产生输出信号。

    SEMICONDUCTOR MEMORY APPARATUS AND INPUT BUFFER THEREFOR
    26.
    发明申请
    SEMICONDUCTOR MEMORY APPARATUS AND INPUT BUFFER THEREFOR 审中-公开
    半导体存储器和输入缓冲器

    公开(公告)号:US20160163363A1

    公开(公告)日:2016-06-09

    申请号:US14625878

    申请日:2015-02-19

    Applicant: SK hynix Inc.

    Inventor: Jin Ha HWANG

    CPC classification number: G11C7/1084

    Abstract: A semiconductor memory apparatus may include an input buffer configured to receive an external signal, boost the external signal to a frequency according to an operation mode signal, and generate an internal signal; and an internal circuit configured to operate by receiving the internal signal.

    Abstract translation: 半导体存储装置可以包括:输入缓冲器,被配置为接收外部信号,根据操作模式信号将外部信号升压到频率,并产生内部信号; 以及内部电路,被配置为通过接收内部信号进行操作。

    BUFFER CIRCUIT AND SYSTEM HAVING THE SAME
    27.
    发明申请
    BUFFER CIRCUIT AND SYSTEM HAVING THE SAME 有权
    缓冲电路和具有相同功能的系统

    公开(公告)号:US20160072487A1

    公开(公告)日:2016-03-10

    申请号:US14608302

    申请日:2015-01-29

    Applicant: SK hynix Inc.

    Inventor: Jin Ha HWANG

    CPC classification number: H03K5/023 H03L5/00

    Abstract: A buffer circuit includes a power supply voltage detection block which may detect a voltage level of a power supply voltage, a bias generation block which may generate a constant bias signal and a plurality of enable bias signals based on the detection result of the power supply voltage, and an input buffer which may amplify an input signal in response to the constant bias signal and the plurality of enable bias signals.

    Abstract translation: 缓冲电路包括可以检测电源电压的电压电平的电源电压检测块,可产生恒定偏置信号的偏置产生块和基于电源电压的检测结果的多个使能偏置信号 以及可以响应于恒定偏置信号和多个使能偏置信号而放大输入信号的输入缓冲器。

    RECEIVER CIRCUIT OF SEMICONDUCTOR APPARATUS
    28.
    发明申请
    RECEIVER CIRCUIT OF SEMICONDUCTOR APPARATUS 有权
    半导体器件接收电路

    公开(公告)号:US20160006418A1

    公开(公告)日:2016-01-07

    申请号:US14515899

    申请日:2014-10-16

    Applicant: SK hynix Inc.

    Inventor: Jin Ha HWANG

    CPC classification number: H03L7/06 H03K3/356139 H03K3/356191

    Abstract: A receiver circuit of a semiconductor apparatus may include, a latch comprising differential input terminals and differential output terminals. The receiver circuit may also include a control unit configured to selectively reset first and second intermediate nodes coupled between the differential input terminals and the differential output terminals according to previous data.

    Abstract translation: 半导体装置的接收器电路可以包括:锁存器,其包括差分输入端子和差分输出端子。 接收机电路还可以包括控制单元,其被配置为根据先前的数据选择性地复位耦合在差分输入端子和差分输出端子之间的第一和第二中间节点。

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