公开(公告)号：US11675943B2

公开(公告)日：2023-06-13

申请号：US17094743

申请日：2020-11-10

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli

IPC: G06F30/327 ,  G06N20/10 ,  G06N3/084 ,  G06F30/34 ,  G06N20/00 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/04 ,  G06N3/08 ,  G06F115/08 ,  G06N7/01 ,  G06N3/063 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78

CPC classification number: G06F30/327 ,  G06F30/34 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/44505 ,  G06F13/4022 ,  G06F15/7817 ,  G06F2115/08 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.

公开(公告)号：US11360667B2

公开(公告)日：2022-06-14

申请号：US17012501

申请日：2020-09-04

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Giuseppe Desoli ,  Anuj Grover ,  Thomas Boesch ,  Surinder Pal Singh ,  Manuj Ayodhyawasi

IPC: G06F3/06 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US10726177B2

公开(公告)日：2020-07-28

申请号：US16517371

申请日：2019-07-19

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli

IPC: G06F9/455 ,  G06F13/42 ,  G06F30/327 ,  G06N3/04 ,  G06N3/08 ,  G06F30/34 ,  G06N3/063 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78 ,  G06N20/10 ,  G06N7/00 ,  G06F115/08

Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.

公开(公告)号：US11836346B2

公开(公告)日：2023-12-05

申请号：US17742987

申请日：2022-05-12

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Giuseppe Desoli ,  Anuj Grover ,  Thomas Boesch ,  Surinder Pal Singh ,  Manuj Ayodhyawasi

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US11823771B2

公开(公告)日：2023-11-21

申请号：US17158875

申请日：2021-01-26

Applicant: STMicroelectronics International N.V. ,  STMICROELECTRONICS S.r.l.

Inventor： Nitin Chawla ,  Thomas Boesch ,  Anuj Grover ,  Surinder Pal Singh ,  Giuseppe Desoli

IPC: G11C8/04 ,  G06N3/02

CPC classification number: G11C8/04 ,  G06N3/02

Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.

公开(公告)号：US11710032B2

公开(公告)日：2023-07-25

申请号：US18055245

申请日：2022-11-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/063 ,  G06F17/18 ,  G06N3/04 ,  G06N3/08 ,  G06F18/21

CPC classification number: G06N3/063 ,  G06F17/18 ,  G06F18/217 ,  G06N3/04 ,  G06N3/08

Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.

公开(公告)号：US11562115B2

公开(公告)日：2023-01-24

申请号：US15423284

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/04 ,  G06F30/327 ,  G06N20/10 ,  G06N3/08 ,  G06F30/34 ,  G06N20/00 ,  G06N7/00 ,  G06F115/08 ,  G06N3/063 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78

Abstract: Embodiments are directed towards a configurable accelerator framework device that includes a stream switch and a plurality of convolution accelerators. The stream switch has a plurality of input ports and a plurality of output ports. Each of the input ports is configurable at run time to unidirectionally pass data to any one or more of the output ports via a stream link. Each one of the plurality of convolution accelerators is configurable at run time to unidirectionally receive input data via at least two of the plurality of stream switch output ports, and each one of the plurality of convolution accelerators is further configurable at run time to unidirectionally communicate output data via an input port of the stream switch.

公开(公告)号：US11531873B2

公开(公告)日：2022-12-20

申请号：US16909673

申请日：2020-06-23

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli ,  Surinder Pal Singh ,  Carmine Cappetta

IPC: G06N3/063 ,  G06F9/50 ,  H03M7/30

Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.

公开(公告)号：US11507831B2

公开(公告)日：2022-11-22

申请号：US16799671

申请日：2020-02-24

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/08 ,  G06F17/18 ,  G06K9/62 ,  G06N3/04

Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.

公开(公告)号：US10977854B2

公开(公告)日：2021-04-13

申请号：US16280963

申请日：2019-02-20

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06T7/11 ,  G06K9/00 ,  G06T15/08 ,  G06T7/62 ,  G06F16/901 ,  G06F9/38 ,  G06K9/62 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Embodiments of a device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and a data volume sculpting unit, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting unit has a counter, a comparator, and a controller. The data volume sculpting unit is arranged to receive a stream of feature map data that forms a three-dimensional (3D) feature map. The 3D feature map is formed as a plurality of two-dimensional (2D) data planes. The data volume sculpting unit is also arranged to identify a 3D volume within the 3D feature map that is dimensionally smaller than the 3D feature map and isolate data from the 3D feature map that is within the 3D volume for processing in a deep learning algorithm.