公开(公告)号：US20200169459A1

公开(公告)日：2020-05-28

申请号：US16679796

申请日：2019-11-11

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: H04L12/24 ,  H03K19/177 ,  H04L29/06 ,  H04L29/08

Abstract: A hardware configuration circuit can sequentially read data packets from a non-volatile memory. For a first data packet, the circuit is configured to store the configuration data and the address included in the data packet in the register, select a target configuration data client circuit as a function of the address included in the first data packet, transmit a first data signal that includes the configuration data included in the first data packet to the target configuration data client circuit, receive a second data signal that includes configuration data stored in the target configuration data client circuit and the address associated with the target configuration data client circuit, and compare the configuration data and address received from the target configuration data client circuit with the configuration data and address stored in the register.

公开(公告)号：US20200167220A1

公开(公告)日：2020-05-28

申请号：US16693103

申请日：2019-11-22

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: G06F11/07

Abstract: A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.

公开(公告)号：US20190007201A1

公开(公告)日：2019-01-03

申请号：US16022033

申请日：2018-06-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

IPC: H04L9/08 ,  H04L9/14 ,  G06F13/36

Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.

公开(公告)号：US20180357012A1

公开(公告)日：2018-12-13

申请号：US16002534

申请日：2018-06-07

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F9/30

Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.

公开(公告)号：US12190120B2

公开(公告)日：2025-01-07

申请号：US18312237

申请日：2023-05-04

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Roberto Colombo

IPC: G06F9/4401 ,  G06F21/64

Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.

公开(公告)号：US12061530B2

公开(公告)日：2024-08-13

申请号：US17655103

申请日：2022-03-16

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G06F11/22 ,  G06F11/07 ,  G06F11/273

CPC classification number: G06F11/2273 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/2733

Abstract: A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

公开(公告)号：US11921910B2

公开(公告)日：2024-03-05

申请号：US17443497

申请日：2021-07-27

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio

IPC: G06F21/83 ,  G06F9/38 ,  G06F9/445 ,  G06F12/02 ,  G06F21/57 ,  G06F21/64 ,  G06F21/74 ,  G09C1/00 ,  H04L9/32 ,  H04L9/40 ,  H04W4/40 ,  H04W12/03 ,  H04W12/106 ,  H04W12/40

CPC classification number: G06F21/83 ,  G06F9/3816 ,  G06F9/445 ,  G06F12/02 ,  G06F21/57 ,  G06F21/64 ,  G06F21/74 ,  G09C1/00 ,  H04L9/3234 ,  H04W12/106 ,  G06F2212/7209 ,  H04L63/0853 ,  H04W4/40 ,  H04W12/03 ,  H04W12/40

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

公开(公告)号：US20230349969A1

公开(公告)日：2023-11-02

申请号：US18186549

申请日：2023-03-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Roberto Colombo ,  Vivek Mohan Sharma ,  Samiksha Agarwal

IPC: G01R31/317

CPC classification number: G01R31/31703 ,  G01R31/31722

Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

公开(公告)号：US20210382779A1

公开(公告)日：2021-12-09

申请号：US17406910

申请日：2021-08-19

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F11/07 ,  G06F11/10

Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.

公开(公告)号：US11113136B2

公开(公告)日：2021-09-07

申请号：US16289405

申请日：2019-02-28

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10

Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.